Cirrus Logic Inc.

Micron Technology Incorporated

Round Rock Research, LLC

John S Geldman

William Henry Radke

Petro Estakhri

Michael Murray

Martin Ragnar Furuhjelm

Jonathan J Hubert

Son H Ho

Michael George

Joe Chen

John J Schadegg

Tony J Yoon

Wesley G Brewer

Paul M Romano

Larry D King

Bhupendra K Ahuja

Phuc Tran

Maryam Imam

Francisco Pardorla

Palaksha Setty

Petro Estakhrf

Interconnection systems are shown that include communication contacts, and a guide. Configurations are shown with a guide that locates a male portion with respect to a female portion and guides their engagement before any communication contacts are engaged. Configurations are also shown with a guide that includes one or more power contacts.

Interconnection systems

Methods and apparatus for managing data storage in hybrid memory devices utilizing single level and multi-level memory cells. Logical addresses can be distributed between single level and multilevel memory cells based on a frequency of write operations performed. Initial storage of data corresponding to a logical address in memory can be determined by various methods including initially writing all data to single level memory or initially writing all data to multilevel memory. Other methods permit a host to direct logical address writes to single level or multilevel memory cells based on anticipated usage.

Hybrid memory management

Cases for tablet computers and methods are disclosed. An embodiment of one such case has an interface configured to allow the tablet computer to communicate with a removable storage device using a communication protocol not supported by the tablet computer, where the case is configured to contain at least a portion of the tablet computer therein.

Cases for tablet computers and methods

Methods and apparatus for managing data storage in hybrid memory devices utilizing single level and multi level memory cells. Logical addresses can be distributed between single level and multilevel memory cells based on a frequency of write operations performed. Initial storage of data corresponding to a logical address in memory can be determined by various methods including initially writing all data to single level memory or initially writing all data to multilevel memory. Other methods permit a host to direct logical address writes to single level or multilevel memory cells based on anticipated usage.

An apparatus and method for disk sector layout, formatting, reading and writing, is based on a flexible formatter microengine that is driven by parameter lists, which may include commands to dynamically download the microengine's writable control store during disk access operations. This reduces the intervention required by the local microprocessor to support exception handling, including defect management, thus decreasing total access time for typical disk access (format, write or read) operations. This also reduces or eliminates the area on the disk required for ID fields, thus increasing the storage capacity of disk drives controlled by the present invention. This also increases disk space utilization, thus increasing the storage capacity of a disk drive controlled by using the present invention. Additionally, the invention is based on ID fields that may contain redundant information for increased fault tolerance. Additionally, the invention supports split data fields while minimizing the amount of additional information that the ID fields must contain about the data field split sizes. Alternatively, the invention supports eliminating ID fields entirely with the prior art functions of ID fields taken over by a combination of parameter lists and sector status flags.

Disk drive control without identification fields

An apparatus and method for disk-sector layout, formatting, reading and writing, is based on a flexible formatter microengine that is driven by parameter lists, which may include commands to dynamically down load the microengine's writable control store during disk access operations. This reduces the intervention required by the local microprocessor to support exception handling, including defect management, thus decreasing total access time for typical disk access (format, write or read) operations. This also reduces or eliminates the area on the disk required for ID fields, thus increasing the storage capacity of disk drives controlled by the present invention. This also increases disk space utilization, thus increasing the storage capacity of a disk drive controlled by using the present invention. Additionally, the invention is based on ID fields that may contain redundant information for increased fault tolerance. Additionally, the invention supports split data fields while minimizing the amount of additional information that the ID fields must contain about the data-field split sizes. Alternatively, the invention supports eliminating ID fields entirely with the prior-art functions of ID fields taken over by a combination of parameter lists and sector status flags.

Defect management and split field processing in disk storage systems

The invented controller is the combination of: an intelligent interface to a SCSI bus, a multi-port buffer memory manager, a formatter, and a local processor port. With the addition of a few components for the device-level interface, the invented controller along with a buffer RAM, a local processor system, and an optional data separator completes a high performance disk, or other mass storage, controller subsystem. The invention is particularly directed to (1) the dual use of a buffer memory as data buffer storage and for storage of instructions to be executed by a SCSI-protocol processor, (2) the architecture of the interface to the SCSI bus, and (3) the instruction set of the SCSI-protocol processor.

Flexible processor-driven SCSI controller with buffer memory and local

An integrated circuit controls the low level, electromechanical functionality of a computer mass storage device, such as a magnetic disk drive incorporating a spindle motor for rotatably controlling a disk and an actuator for positioning at least one read/write head with respect to the disk, to read or write encoded data configured in information data sectors and to sense encoded data of servo data sectors. A servo subsystem is coupled to an output of the read/write head for detecting the servo data sectors and providing a control signal in response thereto. An analog-to-digital subsystem is also coupled to an output of the read/write head and is operative in response to the servo subsystem control signal for converting the encoded data of the servo data sectors to digital transducer position information representative of a position of the read/write head with respect to the data tracks. A data processing subsystem is coupled to the analog-to-digital subsystem for processing the digital transducer position information and providing digital motion control signals in response thereto. A digital-to-analog subsystem is coupled to the data processing subsystem for providing analog control signals to the spindle motor and the actuator in response to the digital motion control signals.

Integrated circuit servo system control for computer mass storage device

The invented controller is the combination of: an intelligent interface to a SCSI bus, a multi-part buffer memory manager, a formatter, and a local processor port. With the addition of a few components for the device-level interface, the invented controller along with a buffer RAM, a local processor system, and an optional data separator completes a high performance disk, or other mass storage, controller subsystem. The invention is particularly directed to (1) the dual use of a buffer memory as data buffer storage and for storage of instructions to be executed by a SCSI-protocol processor, (2) the architecture of the interface to the SCSI bus, and (3) the instruction set of the SCSI-protocol processor.

Flexible processor-driven control of SCSI buses utilizing tags appended

A network for detection and correction of errors in a digital signal data stream, using an encoded code remainder that augments the data stream. The network utilizes a linear shift feedback register and a data register that works as a shifter or as a counter in assisting the error detection/correction process. Although the digital signal is in the form of serial data, the data register works with bytes, rather than bits, in a parallel arrangement so that the processing time is substantially reduced.

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Los Gatos, CA, United States of America

John S Geldman