International Business Machines Corporation

Intermolecular, Inc.

Roche Sequencing Solutions, Inc.

Globalfoundries Inc.

Roche Molecular Systems, Inc.

Genia Technologies, Inc.

Other

Advanced Micro Devices Corporation

Roche Diagnostics Gmbh

F. Hoffmann-la Roche Ag

John S Foster

Olov B Karlsson

Moris Musa Dovek

Andrew M Homola

Thomas R Albrecht

Anh Duong

Robert A Yuan

Hui Tian

Kurt A Rubin

Christopher S Gudeman

Randall W Davis

Roger Chen

Amol Ramesh Joshi

Edward Shian Liu

Cynthia Ann Cech

Zhendong Hong

Andrew Trans

Ruilong Xie

Paul Raymond Besser

Andres Bryant

Bin Yang

Dipankar Pramanik

Muthumanickam Sankarapandian

Stephan Kronholz

Yue-Song He

Pirooz Parvarandeh

Jane Elizabeth Frommer

Sean Xuan Lin

Kenneth Allen Honer

Mark V Raymond

Sean Barstow

Daniel Rugar

Linden James Crawforth

Clemens Fitz

Berthold Reimer

Timothy C O'Sullivan

Janusz B Wojtowicz

Jason Komadina

Morgan Mager

Usha Raghuram

Bei Li

Gregory Nowling

James Mavrinac

Jaquelin K Spong

Eric Takeshi Harada

James Pollard

Luis P Franco

Anne Aguirre

Gerard H Vurens

Kim Van Berkel

Li-Ju J Lin

George L Best

Jiahua Huang

Markus Wallgren

Randall T Kerth

Joanna Wasyluk

Charlene Chen

Patrick C Arnett

Jingang Su

Erich Sawatzky

Sven Metzger

Wing Kei Au

Marowen Ng

Donald K Lam

Ronald L Cicero

Guojun Chen

Janusz B Wójtowicz

Jon A Iwata

Wing Au

Kenneth A Honer

A nanopore cell includes a conductive layer. The nanopore cell further includes a titanium nitride (TiN) working electrode disposed above the conductive layer. The nanopore cell further includes insulating walls disposed above the TiN working electrode, wherein the insulating walls and the TiN working electrode form a well into which an electrolyte may be contained. In some embodiments, the TiN working electrode comprises a spongy and porous TiN working electrode that is deposited by a deposition technique with conditions tuned to deposit sparsely-spaced TiN columnar structures or columns of TiN crystals above the conductive layer.

Use of titanium nitride as an electrode in non-faradaic electrochemical cell

A nanopore cell includes a conductive layer and a working electrode disposed above the conductive layer and at the bottom of a well into which an electrolyte may be contained, such that at least a portion of a top base surface area of the working electrode is exposed to the electrolyte. The nanopore cell further includes a first insulating wall disposed above the working electrode and surrounding a lower section of a well, and a second insulating wall disposed above the first insulating wall and surrounding an upper section of the well, forming an overhang above the lower section of the well. The upper section of the well includes an opening that a membrane may span across, and wherein a base surface area of the opening is smaller than the at least a portion of the top base surface area of the working electrode that is exposed to the electrolyte.

Small aperture large electrode cell

A nanopore cell is disclosed. The nanopore cell includes an electrolyte well having a bottom base, a surrounding sidewall, and a hydrophobic surface above the surrounding sidewall. The nanopore cell further includes a first layer of electrode material disposed on the bottom base of the electrolyte well. The nanopore cell further includes a second layer of electrode material disposed on the surrounding sidewall of the electrolyte well and electrically connected to the first layer of electrode material. The first layer of electrode material and the second layer of electrode material are configured to jointly provide capacitive coupling when an electrolyte is placed in the electrolyte well.

Electrochemical cell with increased current density

A nanopore cell may include a well having a working electrode at a bottom of the well. The well may be formed within a dielectric layer, where the sidewalls of the well may be formed of the dielectric or other materials coating the walls of the dielectric layer. Various materials having different hydrophobicity and hydrophilicity can be used to provide desired properties of the cell. The nanopore in the nanopore cell can be inserted in a membrane formed over the well. Various techniques can be used for providing a desired shape and other properties e.g., of materials and processes for forming the well.

Nanopore well structures and methods

A nanopore cell includes a titanium nitride (TiN) counter electrode configured to be at a first electric potential. The nanopore cell also include a working electrode configured to be at a second electric potential and an insulating wall. The insulating wall and the working electrode form at least a portion of a well configured to contain an electrolyte at a voltage that is at least a portion of an electric potential difference between the first electric potential of the titanium nitride counter electrode and the second electric potential of the working electrode.

Use of titanium nitride as a counter electrode

A biochip for molecular detection and sensing is disclosed. The biochip includes a substrate. The biochip includes a plurality of discrete sites formed on the substrate having a density of greater than five hundred wells per square millimeter. Each discrete site includes sidewalls disposed on the substrate to form a well. Each discrete site includes an electrode disposed at the bottom of the well. In some embodiments, the wells are formed such that cross-talk between the wells is reduced. In some embodiments, the electrodes disposed at the bottom of the wells are organized into groups of electrodes, wherein each group of electrodes shares a common counter electrode. In some embodiments, the electrode disposed at the bottom of the well has a dedicated counter electrode. In some embodiments, surfaces of the sidewalls are silanized such that the surfaces facilitate the forming of a membrane in or adjacent to the well.

Process for biosensor well formation

Provided are methods for fabricating transistors using a gate last approach. These methods involve etching of titanium nitride and titanium carbide structures while preserving high k-dielectric structures. The titanium carbide structures may also include aluminum. Etching may be performed in one or more etching solutions, each including hydrogen peroxide. Titanium nitride and titanium carbide structures can be etched simultaneously (non-selectively) in the same etching solution that also includes hydrochloric acid, in addition to hydrogen peroxide, and maintained at about 25&#xb0; C. and 85&#xb0; C. In some embodiments, titanium nitride structures and titanium carbide structures may be etched separately (selectively) in different operations and using different etching solutions. The titanium nitride structures may be etched in a diluted hydrogen peroxide solution maintained at about 25&#xb0; C. and 85&#xb0; C. The titanium carbide structures may be etched in a solution that also includes ammonium hydroxide, in addition to hydrogen peroxide, and maintained at about 25&#xb0; C.

Solution based etching of titanium carbide and titanium nitride structures

Two-step process sequences uniformly etch both tungsten-based and titanium-based structures on a substrate. A sequence of wet etches using peroxide and heated nitric acid uniformly recesses a metal stack that includes W, TiN, and TiAl. W, TiN and TiC are uniformly recessed by a peroxide etch at &#x2dc;25 C followed by an acid solution with a very small amount of added peroxide at &#x2dc;60 C. TiC is etched without etching trench oxides or other metals in a work-function metal stack by either (1) highly-dilute of ultra-dilute HF at 25-35 C, (2) dilute HCl at 25-60 C, (3) dilute NHOH at 25-60 C, or (4) solution (2) or (3) with small amounts of peroxide. Other metals in the stack may then be plasma-etched without being blocked by TiC residues.

Etching of semiconductor structures that include titanium-based layers

Combinatorial workflow is provided for evaluating cleaning processes after forming a gate structure of transistor devices, to provide optimized process conditions for gate stack formation, including metal gate stack using high-k dielectrics. NMOS and PMOS transistor devices are combinatorially fabricated on multiple regions of a substrate, with each region exposed to a different cleaning chemical and process. The transistor devices are then characterized, and the data are compared to categorize the potential damages of different cleaning chemicals and processes. Optimized chemicals and processes can be obtained to satisfy desired device requirements.

High productivity combinatorial workflow for post gate etch clean development

The invention discloses a method for cleaning residues from a semiconductor substrate during a nickel platinum silicidation process. Post silicidation residues of nickel and platinum may not be removed adequately just by an aqua regia solution (comprising a mixture of nitric acid and hydrochloric acid). Therefore, embodiments of the invention provide a multi-step residue cleaning, comprising exposing the substrate to an aqua regia solution, followed by an exposure to a chlorine gas or a solution comprising dissolved chlorine gas, which may further react with remaining platinum residues, rendering it more soluble in aqueous solution and thereby dissolving it from the surface of the substrate.

Process to remove Ni and Pt residues for NiPtSi application using chlorine gas

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Morgan Hill, CA, United States of America

John S Foster