International Business Machines Corporation

John S Austin

Ram Kelkar

Pradeep Thiagarajan

Kai D Feng

Zhenrong Jin

Shiu Chung Ho

Michael Richard Ouellette

Douglas Willard Stout

Stephen Dale Wyatt

Charles Joseph Masenas

Ilya I Novof

Ronald A Piro

Donald E Strayer

Matthew T Sobel

Melissa A Beacom

A dynamic latch has a pair of parallel pass gates (a first parallel pass gate that receives a seed signal, and a second parallel pass gate that receives a data signal). A first latch logic circuit performs logic operations using signals output by the parallel pass gates to produce an updated data signal. An additional pass gate is operatively connected to the first latch logic circuit. An additional pass gate controls passage of the updated data signal. An inverter receives the updated data signal from the pass gate, and inverts and outputs the updated data signal as an output data signal. Thus, the dynamic latch comprises two inputs into the pair of parallel pass gates and performs only one of four logical operations on a received data signal. The four logical operations are performed using the signals applied to the two inputs.

High frequency CMOS programmable divider with large divide ratio

A phase lock loop (PLL) includes a PLL feedback circuit having a feedback divider. The feedback divider has a first dynamic latch, a first logic circuit, and a plurality of serially connected dynamic latches. Each of the serially connected dynamic latches receives and forwards additional data signals to subsequent ones of the serially connected dynamic latches in series. The second-to-last dynamic latch in the series outputs a fourth data signal to a last dynamic latch in the series. The last dynamic latch receives the fourth data signal and outputs a fifth data signal. A first feedback loop receives the fourth data signal from the second-to-last dynamic latch and the fifth data signal from the last dynamic latch. The first feedback loop comprises a NAND circuit that combines the fourth and fifth data signals and the first feedback loop outputs the first feedback signal.

Phase lock loop having high frequency CMOS programmable divider with large divide ratio

A selectable latch has a pair of parallel pass gates (a first parallel pass gate that receives a seed signal, and a second parallel pass gate that receives a data signal). A first latch logic circuit performs logic operations using signals output by the parallel pass gates to produce an updated data signal. An additional pass gate is operatively connected to the first latch logic circuit. An additional pass gate controls passage of the updated data signal. The output of the parallel pass gates and the additional pass gate is connected to a feedback loop. The feedback loop operates as a dynamic latch for high frequency applications or as a static latch for low frequency applications. Thus, the selectable latch comprises two inputs into the pair of parallel pass gates and performs only one of four logical operations on a received data signal.

Selectable dynamic/static latch with embedded logic

A method for dividing a high-frequency signal. The method including: generating, from a first clock signal, a second clock signal, the second clock cycle time greater than the first clock cycle time, an off-time of one cycle of the second clock signal being one first clock cycle time less than an on-time of one cycle of the second clock signal; shifting in time the second clock signal by half of a first clock cycle time to generate a third clock signal, the second clock cycle time equal to the third clock cycle time; performing a logical AND of the second clock signal and the third clock signal to generate a fourth clock signal, the third clock cycle time equal to the fourth clock cycle time, an on-time of one cycle of the fourth clock signal equal to an off-time of one cycle of the fourth clock signal.

Method for dividing a high-frequency signal

Several latch circuits including a NAND gate stage and combinations of clocked inverter stages and inverter stages are described. A programmable frequency divider including homologue frequency divider circuits using the latch circuits is also described. Also described is a circuit included in the homologue frequency divides and a method for correcting the duty cycle of clock signals generated by the homologue frequency dividers to 50%.

Programmable low-power high-frequency divider

A fast latch including: a NAND stage adapted to receive a clock signal and a data input signal; a clocked inverter stage, a first input of the clocked inverter stage coupled to the output of the NAND stage and a second input of the clocked inverter stage coupled to the clock signal; a first inverter stage, a first input of the first inverter stage coupled to an output of the clocked inverter and a second input of the first inverter stage coupled to a reset signal; and a second inverter stage, having an output, an input of the second inverter stage coupled to an output of the first inverter stage. The fast latch is suitable for use in frequency divider circuits also described. A homologue of frequency dividers using the fast latch, a unique 3/4 divider and a 2 divider not using the fast latch are also disclosed.

A voltage-controlled oscillator (VCO) comprising an odd number of delay stage circuits. Each delay stage circuit operates between supply voltages VDD and VSS (VDD&#x3e;VSS) and comprises (1) an input node, (2) an output node, (3) an inverting circuit, and (4) an electric discharge path coupling the output node to VSS. The electric discharge path includes a switch circuit and a resistance adjusting circuit electrically coupled in series between the output node and VSS. In response to an input signal rising at the input node, the inverting circuit decreases an output signal at the output node, and the electric discharge path opens to help pull the output signal down faster. In response to an input signal falling at the input node, the inverting circuit increases the output signal at the output node, and the electric discharge path closes to minimize its own effect.

Voltage-controlled oscillators having controlling circuits

A programmable frequency divider circuit with symmetrical output is disclosed. The frequency divider includes a non-symmetrical LFSR based component operated in series with a symmetrical divider component. Both the LFSR and the symmetrical divider may be programmed to provide flexibility. The frequency divider can dynamically adjust the divisor of the LFSR component to overcome limitations in the divide resolution due to the series combination of dividers, providing even and odd divisor values. The divider architecture can also provide higher level functions, including synchronization of multiple divider outputs, dynamic switching of divisor values and generation of multi-phased and spaced outputs. The linear feedback shift register (LFSR) component includes a feedback logic network decomposed into multiple stages to realize a maximum latch-to-latch operational latency of one gate delay regardless of the size of the LFSR.

Programmable frequency divider with symmetrical output

A non-integer frequency divider is disclosed. The non-integer frequency divider circuit includes several base stages connected to each other. The non-integer frequency divider circuit also includes a clocking circuit for passing an enable bit from one of the base stages to another such that only one of the base stages is enabled at any give time. The enable bit has a pulse width of one clock cycle. The outputs from the base stages are grouped together by an OR gate to generate a single output that is a fraction of an input clock signal.

Non-integer frequency divider circuit

A programmable, self-resetting divider includes a modified Linear Feedback Shift Register (LFSR) counter that starts in an initial state and increments through a count range. The self-resetting divider also includes a reset circuit that detects a pre-selected final state of the modified LFSR counter, provides an output signal in response to the detecting of the final state, and provides a reset signal to the modified LFSR counter in response to the detecting of the final state.

Programmable, self-resetting divider

A programmable divider circuit having an adjustable shift register is coupled to a clock and to an output. The shift register receives a clock signal having a clock signal frequency and outputs an output signal with an output frequency corresponding to a user selected divide ratio of the clock signal frequency. Control inputs are coupled to the adjustable shift register to receive control data for adjusting a length of the shift register, the length of the shift register corresponding to the user selected divide ratio.

Asynchronously programmable frequency divider circuit with a symmetrical

A phase locked loop circuit is provided which includes a phase/frequency detector which uses a divider circuit and feedback from a clock distribution tree to generate INC and DEC pulses which do not have 'dead zones'. A pair of charge pumps receives the INC and DEC pulses. One charge pump is a differential pump and has a voltage controlled common mode feedback circuit to maintain a common mode controlled voltage. A differential current is outputted to a loop filter capacitor by this charge pump. The other charge pump is a single-ended output pump which supplies current to a current controlled oscillator which also receives input from a voltage to current converter. The current controlled oscillator includes a variable resistance load which varies inversely with the magnitude of the input current. A jitter control circuit is also provided which reduces jitter in the current controlled oscillator output in the locked phase. Also, a lock indicator is provided which is time independent, and provides a lock indication when the loop enters the locked condition.

Growing community of inventors

Winooski, VT, United States of America

John S Austin