Hewlett-packard Development Company, L.p.

John S Atkinson

Michael John Erickson

Paul John Mantey

Robert J Blakely

Systems, methods and software products ensure correct connectivity between circuit designs. A list of connections of the circuit designs is generated. One or more mapping files are generated from the list to correlate connections between the circuit designs. The mapping file is regenerated in response to modification of at least one of the circuit designs. Optionally, at least one schematic associated with at least one of the circuit designs is regenerated using information in the regenerated mapping file

Systems and methods for ensuring correct connectivity between circuit designs

The system of the invention ensures pin assignments between system board connections of printed circuit boards. A plurality of software configuration files define connections of a plurality of printed circuit boards. A mapping file correlates pin assignment attributes between the software configuration files. A processing section processes the configuration files and the mapping file to generate board schematics for the plurality of printed circuit boards with common pin assignment for the connections of each of the printed circuit boards. The software configuration files may include symbol files representing parts within the plurality of printed circuit boards. The software configuration files may include geometry files representing physical attributes of the parts. Changes to the design are automatically correlated to pin assignments through the boards and layout.

System for ensuring correct pin assignments between system board connections using common mapping files

Method for ensuring correct pin assignments between system board connections using common mapping files

A capacitor mounting method and resulting printed circuit board that increases the mounting density of both vias and decoupling capacitors is presented. Vias are shared between capacitors mounted on the top and bottom of the printed circuit board. This arrangement allows increased decoupling capacitor density and avoids the current doubling problem when shared vias are connected with capacitors installed on the same side of the board.

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Fort Collins, CO, United States of America

John S Atkinson