Parthus Ireland Limited

Amadala Limited

John Ryan

John M Horan

Ciaran Cahill

Niall O'Donovan

David J Foley

Tholom Kiely

Mark M Smyth

Steven Dunphy

Mark Smyth

Kay Hearne

A method that automatically generates a design for an analog phase lock loop (PLL) core in response to a desired clock frequency.

Method and apparatus for automatically generating a phase lock loop (PLL)

An apparatus is described comprising a current source and a pair of transistors coupled to the current source. A pair of variable loads are coupled to the pair of transistors such that a first of the pair of transistors drives a first of the pair of variable loads and a second of the pair of transistors drives a second of the pair of variable loads. Each of the pair of variable loads are coupled to a high gain input and a low gain input. Another apparatus is described comprising an oscillator having a high gain input and a low gain input. The oscillator comprises a series of inverters where each inverter output is coupled to the next inverter input in the series. At least one of the inverters comprises a current source and a pair of transistors coupled to the current source. A pair of variable loads are coupled to the pair of transistors such that a first of the pair of transistors drives a first of the pair of variable loads and a second of the pair of transistors drives a second of the pair of variable loads. Each of the pair of variable loads are coupled to a high gain input and a low gain input. Yet another apparatus is described comprising an oscillator having a high gain input and a low gain input. The oscillator comprises a series of inverters, each inverter output is coupled to the next inverter input in the series. The low gain input is coupled to less than all of the inverters within the series.

Method and apparatus for PLL with improved jitter performance

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Rochestown, Ireland

John Ryan