Gan Systems Inc.

John Roberts

Greg P Klowak

Ahmad Mizan

Girvan Patterson

Cameron Mcknight-Macneil

Hugues Lafontaine

Iain H Scott

Greg Klowak

An integrated gate protection device P for a GaN power transistor Dprovides negative ESD spike protection. Protection device P comprises a smaller gate width wenhancement mode GaN transistor Pm. The source of Pm is connected to its gate, the drain of Pm is connected to the gate input of D, and the source of Pm is connected to the intrinsic source of D. When the gate input voltage is taken negative below the threshold voltage for reverse conduction, Pm conducts and quenches negative voltage spikes. When device P comprises a plurality of GaN protection transistors Pto Pn, connected in series, it turns on when the gate input voltage applied to the drain of Pgoes negative by more than the sum of the threshold voltages of Pto Pn. The combined gate width of Pto Pn is selected to limit the gate voltage excursion of D

Gate input protection for devices and systems comprising high power E-mode GaN transistors

Devices and systems comprising high current/high voltage GaN semiconductor devices are disclosed. A GaN die, comprising a lateral GaN transistor, is sandwiched between an overlying header and an underlying composite thermal dielectric layer. Fabrication comprises providing a conventional GaN device structure fabricated on a low cost silicon substrate (GaN-on-Si die), mechanically and electrically attaching source, drain and gate contact pads of the GaN-on-Si die to corresponding contact areas of conductive tracks of the header, then entirely removing the silicon substrate. The exposed substrate-surface of the epi-layer stack is coated with the composite dielectric thermal layer. Preferably, the header comprises a ceramic dielectric support layer having a CTE matched to the GaN epi-layer stack. The thermal dielectric layer comprises a high dielectric strength thermoplastic polymer and a dielectric filler having a high thermal conductivity. This structure offers improved electrical breakdown resistance and effective thermal dissipation compared to conventional GaN-on-Si device structures.

GaN semiconductor device structure and method of fabrication by substrate replacement

An electronic switching system and device comprising driver circuits for power transistors are disclosed, with particular application for MOSFET driven, normally-on gallium nitride (GaN) power transistors. Preferably, a low power, high speed CMOS driver circuit with an integrated low voltage, lateral MOSFET driver is series coupled, in a hybrid cascode arrangement, to a high voltage GaN HEMT and provides for improved control of noise and voltage transients. Monitoring and control functions, including latching and clamping, are based on monitoring of Vconditions for shut-down and start-up conditioning to enable safer operation, particularly for high voltage and high current switching. Preferred embodiments also provide isolated, self-powered, high speed driver devices, with reduced input losses.

Devices and systems comprising drivers for power conversion circuits

Power switching systems are disclosed comprising driver circuitry for enhancement-mode (E-Mode) GaN power transistors with low threshold voltage. Preferably, a GaN power switch (D) comprises an E-Mode high electron mobility transistor (HEMT) with a monolithically integrated GaN driver. Dis partitioned into sections. At least the pull-down and, optionally, the pull-up driver circuitry is similarly partitioned as a plurality of driver elements, each driving a respective section of DEach driver element is placed in proximity to a respective section of Dreducing interconnect track length and loop inductance. In preferred embodiments, the layout of GaN transistor switch and the driver elements, dimensions and routing of the interconnect tracks are selected to further reduce loop inductance and optimize performance. Distributed driver circuitry integrated on-chip with one or more high power E-Mode GaN switches allows closer coupling of the driver circuitry and the GaN switches to reduce effects of parasitic inductances.

Distributed driver circuitry integrated with GaN power transistors

Embedded packaging for devices and systems comprising lateral GaN power transistors is disclosed. The packaging assembly is suitable for large area, high power GaN transistors and comprises an assembly of a GaN power transistor and package components comprising a three level interconnect structure. In preferred embodiments, the three level interconnect structure comprises an on-chip metal layer, a copper redistribution layer and package metal layers, in which there is a graduated or tapered contact area sizing through the three levels for dividing/applying current on-chip and combining/collecting current off-chip, with distributed contacts over the active area of the GaN power device. This embedded packaging assembly provides a low inductance, low resistance interconnect structure suitable for devices and systems comprising large area, high power GaN transistors for high voltage/high current applications.

Embedded packaging for devices and systems comprising lateral GaN power transistors

Driver circuitry for switching systems comprising enhancement mode (E-Mode) GaN power transistors with low threshold voltage is disclosed. An E-Mode high electron mobility transistor (HEMT) Dhas a monolithically integrated GaN driver, comprising smaller E-Mode GaN HEMTs Dand D, and a discrete dual-voltage pre-driver. In operation, Dprovides the gate drive voltage to the gate of the GaN switch D, and Dclamps the gate of the GaN switch Dto the source, via an internal source-sense connection closely coupling the source of Dand the source of D. An additional source-sense connection is provided for the pre-driver. Boosting the drive voltage to the gate of Dproduces firm and rapid pull-up of Dand Dfor improved switching performance at higher switching speeds. High current handling components of the driver circuitry are integrated with the GaN switch and closely coupled to reduce inductance, while the discrete pre-driver can be thermally separated from the GaN chip.

Power switching systems comprising high power e-mode GaN transistors and driver circuitry

A semiconductor device in provided having a substrate and a semiconductor layer formed on a main surface of the substrate. A plurality of first island electrodes and a plurality of second island electrodes are placed over the semiconductor layer. The plurality of first island electrodes and second island electrodes are spaced apart from each other so as to be alternatively arranged to produce two-dimensional active regions in all feasible areas of the semiconductor layer. Each side of the first island electrodes is opposite a side of the second island electrodes. The semiconductor device can also include a plurality of strip electrodes that are formed in the regions between the first island electrodes and the second island electrodes. The strip electrodes serve as the gate electrodes of a multi-island transistor. The first island electrodes serve as the source electrodes of the multi-island transistor. The second island electrodes serve as the drain electrodes of the multi-island transistor. A plurality of connections to the gate electrodes are provided at each interstice defined by corners of the first island electrodes and the second island electrodes.

Gallium nitride power devices using island topography

Devices and systems comprising driver circuits are disclosed for MOSFET driven, normally-on gallium nitride (GaN) power transistors. Preferably, a low power, high speed CMOS driver circuit with an integrated low voltage, lateral MOSFET driver is series coupled, in a hybrid cascode arrangement to a high voltage GaN HEMT, for improved control of noise and voltage transients. Co-packaging of a GaN transistor die and a CMOS driver die using island topology contacts, through substrate vias, and a flip-chip, stacked configuration provides interconnections with low inductance and resistance, and provides effective thermal management. Co-packaging of a CMOS input interface circuit with the CMOS driver and GaN transistor allows for a compact, integrated CMOS driver with enhanced functionality including shut-down and start-up conditioning for safer operation, particularly for high voltage and high current switching. Preferred embodiments also provide isolated, self-powered, high speed driver devices, with reduced input losses.

Devices and systems for power conversion circuits

A gallium nitride (GaN) device that has greatly superior current handling ability per unit area than previously described GaN devices. The improvement is due to improved layout topology. The layout scheme, which uses island electrodes rather than finger electrodes, is shown to increase the active area density over that of conventional interdigitated structures. Ultra low on resistance transistors can be built using the island topology. Specifically, the present invention, which uses conventional GaN lateral technology and electrode spacing, provides a means to enhance cost/effective performance of all lateral GaN structures.

Island matrixed gallium nitride microwave and power switching transistors

A Gallium Nitride (GaN) series of devices&#x2014;transistors and diodes are disclosed&#x2014;that have greatly superior current handling ability per unit area than previously described GaN devices. The improvement is due to improved layout topology. The devices also include a simpler and superior flip chip connection scheme and a means to reduce the thermal resistance. A simplified fabrication process is disclosed and the layout scheme which uses island electrodes rather than finger electrodes is shown to increase the active area density by two to five times that of conventional interdigitated structures. Ultra low on resistance transistors and very low loss diodes can be built using the island topology. Specifically, the present disclosure provides a means to enhance cost/effective performance of all lateral GaN structures.

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Kanata, Canada

John Roberts