International Computers Limited

Stc, Inc

John Richard Eaton

Kevin Hughes

Colin Martin Duxbury

Philip V Rose

George Allt

Nicholas Peter Holt

Peter L Desyllas

Barry Gordon Radley

John E Murray

Alasdair Rawsthorne

A computer system in which blocks of source code instructions are translated into blocks of target code instructions and executed. During execution, the system builds up dynamic behavior information about frequency of execution of, and relationships between, the blocks. On the basis of this information, a block coalition mechanism selects blocks, and combines them to form an optimized superblock of target code instructions that is functionally equivalent to the combination of the selected blocks. In this way, the system can start with relatively small, naively translated blocks, and build up larger, more optimized blocks, on the basis of the dynamic behavior of the code.

Instruction execution mechanism

A method of translating source code instructions into target code instructions is described. Prior to translate time, an existing interpreter is analyzed to identify sequences that implement individual source order code instructions. Sub-sequences within each template that implement predetermined sub-functions are identified and eliminated. The sequences are compiled and stored as templates. For each instruction in an input block of source code instructions, the appropriate template for that source code instruction is selected and appended to an output block of target code instructions. The source code block is then analyzed to determine the net effect of the non-implemented sub-functions, and code is planted in the output block to achieve this net effect.

Instruction translation method

A data processing system comprises a number of processing nodes interconnected by a data transmission network. The network is 'hairpin' shaped, having a first leg, a second leg, and a loopback connection connecting the first leg to the second leg. Each node sends public write messages on to the first leg, and receives messages from the second leg. All the messages flow through the loopback connection, which thus serves as a central chronology point for the system, defining a unique chronological order for the messages. The network can be reconfigured, to split it into a number of sub-networks, each with first and second legs interconnected by a loopback connection. The system may include a backup node, for disaster recovery, situated at a very long distance from the processing nodes.

Multi-node data processing system

An apparatus for adding two BCD numbers, avoids the need for special adders with detection of carries between BCD digits. First, a sum without carries is generated, by forming the binary sum of the two numbers and an all-sixes pattern, without any carries between BCD digits. Next, a sum with carries is generated, by forming the binary sum of the two numbers and an all-sixes pattern, with carries between BCD digits. A mask pattern is then generated, comprising a six in each BCD digit where the sum without carries is unequal to the sum with carries. A result is then generated by forming the binary sum of the two numbers and the mask pattern, with carries between BCD digits.

Decimal arithmetic apparatus and method

A data processing apparatus, having a visible register map for associating physical registers with logical registers. Instructions involving register-to-register transfers are executed by altering the association between the physical registers and the logical registers, without actually transferring data between the registers, so as to avoid logically redundant operations and to take such instructions out of the critical path of execution.

Data processing apparatus with improved mechanism for executing

A method and apparatus as described for predicting the performance of a computer system. A benchmark program is run on an existing host computer, and is monitored to determine the actual sequence of instructions in the instruction set of the host. These are then converted into the corresponding sequence in the instruction set of the target. The performance of the target system in executing these instructions is then determined.

Method of predicting the performance of an emulated computer system

A data processor is provided with a mechanism for controlling its performance. The processor is allowed to run normally for R clock beats, and then further instruction starts are inhibited for W clock beats. The ratio W/R determines the level of performance of the processor.

Performance control mechanism for alternately allowing instructions to

Data processing apparatus comprises a series of pipeline units each of which consists of a number of pipeline stages. The units are interconnected by a number of parameter files, which provide a number of slots. Whenever an instruction is initiated in the pipeline, it is allocated a slot, and retains that slot until its execution is successfully completed. Two independent streams of instructions are scheduled through the pipeline, each being allocated a fixed number of the slots. In normal operation, one of the streams has priority over the other stream. An instruction is allowed to change the process state only when it successfully terminates at the end of the pipeline, thus ensuring consistency. An instruction can be started in a lower pipeline unit as soon as it is know that its required operand will be available in time from the data slave, thus allowing the operations of these two units to be overlapped.

Pipelined data processor with parameter files for passing parameters

In a pipelined data processor, when a dependency is detected between a first instruction and a second, subsequent instruction, the second instruction is abandoned. A look-ahead mode of operation is then initiated, in which instructions subsequent to the abandoned instruction are allowed to continue to be executed so as to pre-fetch operands, but are not allowed to be fully executed. The processor has two separate streams of instructions, each of which streams can be independently put into look-ahead mode. When one stream is in look-ahead mode, the other is given priority.

Pipelined processor with look-ahead mode of operation

A microprogrammed processor in which instructions have alternative fast and slow microprogram sequences. The fast sequences are designed for speed, and can detect exception conditions but do not resolve them. The slow sequences perform all the necessary tests to resolve these conditions. When a fast sequence detects an exception, that sequence is abandoned, and the corresponding slow sequence is run.

Microprogram controlled data processing apparatus

A data processing apparatus, which includes a microprogram control unit for producing control signals for the apparatus. Each microinstruction contains a number of control bits, and an address field. The address field addresses a control memory so as to read out a control word. Each control word specifies the way in which the control signals are mapped on to the control bits of the microinstruction. The output of the control memory controls switching logic which connects the control bits to the specified control signal lines. This variable mapping of the control signals allows the control signals to be packed into any available space in the microinstruction, thus reducing the required number of bits in the microinstruction without any significant loss of flexibility. Certain critical control signals however are derived from fixed positions in the microinstruction so as to avoid delays. These critical control signals are confirmed by validity signals from the control memory.

Microprogram control apparatus having variable mapping between

A data processing system has a two-level storage system in which data items are copied from a main store into a smaller, faster slave store on demand. The mapping of the main store on to the slave store is a many-to-one mapping so that situations will occur where two required data items cannot both be present simultaneously in the slave store because they map on to the same location. The system has special logic which detects this situation and, upon detection, temporarily suspends the use of the slave store and instead uses a smaller first-in first-out area of storage.

Two level store with many-to-one mapping scheme

A pipelined data processing system having n processing stages, each of which is under the control of a central microprogram. Each microprogram instruction is decoded to produce n control signals, one for each processing stage. Microprogram start addresses are generated by combining information from the latest n program instructions received. Thus, each microprogram sequence implements a combination of phases of successive program instructions. A flag register is used to store relatively static control information, and effectively provides an extension of the microprogram instruction.

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Salford, United Kingdom

John Richard Eaton