Texas Instruments Corporation

Adx Research, Inc.

John Ribe

Pallab Midya

Kevin L Kornher

Roger Griesmer

David J Potts

Brian D Lindemann

Ikram Hussain Syed

A pulse quadrature modulator generates both alpha and beta binary signals, each one serial bit switched at an RF carrier frequency at a fraction of a high speed quantization clock. The alpha and beta binary signals each have respective alpha and beta pulse edges nominally occurring at two times the RF carrier frequency. The alpha and beta pulse edges alternate respectively. The alpha and beta pulse edges are each synchronized to the high speed quantization clock switched based on the baseband I and Q signal inputs. First and second switches gate a power signal using a respective of the alpha or beta binary signals to respectively produce first and second power outputs. The first and second switches differentially drive an RF load such as an antenna across the first and second power outputs having pulse edges at nominally at an integer multiple of four times the RF carrier frequency.

Pulse quadrature modulator and method

This invention addresses difficult issues encountered in simulations and design verification efforts on complex microprocessor/digital signal processor devices. The invention provides a means for monitoring and tracking pending bugs and automates the rejection of already known/pending bugs. This allows developers/debuggers to focus on finding and correcting new bugs. This improves design development efficiency many fold and lets design engineers and verification engineers focus on real, new and unique issues. This is especially true when test cases are generated in a random way and the test case contents are actually unknown.

Pending bug monitors for efficient processor development and debug

A method for testing an integrated circuit using a tester. The tester has internal periods for timing reference. The integrated circuit has one or more input ports, one or more output ports and a logic circuit disposed between the input ports and the output ports. The tester applies an input signal to one or more of the input ports, the input signal being synchronous to the internal periods of the tester, such that, by the operation of the logic circuit, an output signal appears at one or more of the output ports. The method comprises the following steps. First, a first output port is selected having a predetermined signal event that occurs at the first output port during a predetermined time range, the predetermined time range being determined with respect to the internal period. Then, the predetermined signal event is used as a timing reference for a test event of the integrated circuit, the test event occurring a predetermined time interval from the predetermined event.

Method for integrated circuit design and test

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West Chicago, IL, United States of America

John Ribe