Rambus Inc.

Clearspeed Technology Limited

John Rhoades

Ray McConnell

Paul Winser

Ken Cameron

Gordon Faulds

Gajinder Singh Panesar

Jeff Bond

Anthony Spencer

Danny Halamish

Simon McIntosh-Smith

Matthias Dejaegher

Dave Stuttard

Dave Williams

Eamon O'Dea

Phil Atkin

Tim Day

Trey Greer

Russell David

A look up enginecomprising a storage meansfor storing a plurality of entries, each entry comprising a value and an associated key value, such that, in operation, a look up is carried out by outputing a value which is associated with the stored key value which matches an input key value. The look up enginecomprises a plurality of look up state machinesconnected in parallel to enable multiple look ups to be carried out concurrently. Each entry comprises an associated skip value, if the skipped bits of the input key value and the associated skip value mismatches, an error message is output to indicate lookup failure. The entries may be stored in a trie format which is constructed by identifying overlapping ranges between the plurality of entries; splitting the identified overlapping ranges; storing the plurality of entries within a trie structure.

Lookup engine

A data processing architecture includes an input device that receives an incoming stream of data packets. A plurality of processing elements are operable to process data received from the input device. The input device is operable to distribute data packets in whole or in part to the processing elements in dependence upon the data processing bandwidth of the processing elements.

SIMD array operable to process different respective packet protocols simultaneously while executing a single common instruction stream

An input/output system transfers data packets to and from a SIMD array of processing elements (PEs) such that different sizes of data packets are transferred to respective ones of the PEs. The packets are transferred in batches to respective different addresses in the array under the control of the PEs. Transfer to or from the array may be carried out when either a batch or part of a batch is ready for transfer. The decision to transfer either full or part batches is made in dependence upon the speed of the PEs and the speed and intermittency of the data packets.

Data processing architectures for packet handling using a SIMD array

A data processing architecture comprising:

Data processing architectures for packet handling wherein batches of data packets of unpredictable size are distributed across processing elements arranged in a SIMD array operable to process different respective packet protocols at once while executing a single common instruction stream

Data processing architectures

A data processing apparatus includes a SIMD (Single Instruction Multiple Data) array () of processing elements. The processing elements are operably divided into a plurality of processing blocks, the processing blocks being operable to process respective groups of data items.

Memory access consolidation for SIMD processing elements having access indicators

Growing community of inventors

Bristol, United Kingdom

John Rhoades