Ati Technologies Inc.

Ati International Srl

John Raymond Wiseman

Michael G Frank

Glen Timothy McDonnell

A memory controller for use in a computer system. The controller has a buffer having an input configured to receive read and write requests. Each request has an associated memory address. For a selected received request, prior received requests out of a set of the received requests are determined. For each determined prior received request, that request's memory address is compared to the selected request's memory address to see if they match. If a match exists, the selected request is prevented from being memory executed.

Memory request interlock

A data bus bandwidth allocation apparatus and method uses buffer entry feedback data from a buffer, such as an overflow buffer, that receives requested data over an unregulated bus. The data bus bandwidth allocation method and apparatus generates data issue delay data based on the buffer entry feedback data to adjust data commands to a data source, such as frame buffer memory used to feed a regulated bus. In one embodiment, the data issue rate regulator utilizes a programmable threshold corresponding to a threshold of data entries in an overflow. The overflow FIFO has feedback indicating, for example, the number of free entries or the number of full entries. The data issue rate regulator provides data rate regulation information to an adjustable delay sequencer. The adjustable delay sequencer selectively sequences data reads from the frame buffer memory so that data collisions do not occur over the memory read backbone.

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Newtown, PA, United States of America

John Raymond Wiseman