Ericsson Gmbh

Western Digital Technologies, Inc.

John Randall

Gihad Ghaibeh

Victor Avila

Hsing Heng Hsieh

Aspects of a storage device including a memory and a controller are provided for error detection and data integrity checking during the data transfer of write operations. The memory includes a write enable input. The controller generates data integrity information based on at least one data byte to be written to the memory, and transfers the at least one data byte and the data integrity information to the memory, with the data integrity information being transferred to the write enable input. A data integrity circuit receives the at least one data byte and the data integrity information from the controller, and detects whether an error exists in the at least one data byte based on the data integrity information. Accordingly, error detection of data being written to memory may be improved by the data integrity checking of the data prior to being written to the memory of the storage device.

Data integrity check for writing data in memory

A data transmission protocol for use in an ATM-based point-to-multipoint passive optical network having a headend facility and a plurality of downstream network units, wherein downstream data is transmitted in serial data frames comprising one hundred eighty, fifty-four byte downstream slots, including two framing slots and one hundred seventy-eight ATM cell slots, which are transmitted every 125 .mu.sec for an overall downstream bit rate of 622.08 Mbps. Upstream data transmission is provided on a 'permit' basis controlled by the headend based on monitoring ATM cell queue sizes at respective network units, wherein each downstream frame slot includes a one byte MAC overhead header field for transmitting upstream transmission permits allocated over twenty bit permit fields, for a total of seventy-two upstream permits allocated per downstream frame. Upstream data is transmitted from an individual network units in five hundred forty bit upstream data slots, each upstream slot having a preamble portion and a payload portion,--i.e., with seventy-two upstream slots are transmitted every 125 .mu.sec, thereby forming upstream frames received at the headend at a data rate of 311.04 Mbps. Upstream bandwidth permits are based on a selected set of service priorities, wherein the respective permits specify which ATM service type is to be transmitted.

Protocol for data communication over a point-to-multipoint passive

A data transmission protocol for use in an ATM-based point-to-multipoint passive optical network having a headend facility and a plurality of downstream network units, wherein downstream data is transmitted in serial data frames comprising one hundred eighty, fifty-four byte downstream slots, including two framing slots and one hundred seventy-eight ATM cell slots, which are transmitted every 125 .mu.sec for an overall downstream bit rate of 622.08 Mbps. Upstream data transmission is provided on a 'permit' basis controlled by the headend based on monitoring ATM cell queue sizes at respective network units, wherein each downstream frame slot includes a one byte MAC overhead header field for transmitting upstream transmission permits allocated over twenty bit permit fields, for a total of seventy-two upstream permits allocated per downstream frame. Upstream data is transmitted from an individual network units in five hundred forty bit upstream data slots, each upstream slot having a preamble portion and a payload portion, i.e., with seventy-two upstream slots are transmitted every 125 .mu.sec, thereby forming upstream frames received at the headend at a data rate of 311.04 Mbps. Upstream bandwidth permits are based on a selected set of service priorities, wherein the respective permits specify which ATM service type is to be transmitted.

Growing community of inventors

Fremont, CA, United States of America

John Randall