International Telesystems Corporation

John Ramsay

Thomas Ouellette

Richard N Deglin

Thomas Quellette

This invention provides an improved means for communicating between a central communications or computer processor and a plurality of peripheral devices via a serial interface such as a pulse coded modulation (PCM) bus. The processor sends data via one of two redundant communications channels, such as a PCM bus, to the peripheral devices, each of which is equipped with a data receiving means such as a shift register. These data receiving means check a specific character position of the input data for a pattern which is unlikely to occur at random, such as hexadecimal `7E`. (X `7E` has a bit pattern of 0111 1110.) Whenever the specified pattern is detected, a return pattern is generated in a specified character position of the data stream which is periodically sent back to the processor. As long as these return characters are received, the processor continues to send data via the first communications channel, and the receiving peripheral devices continue to read their data from that channel. When the return pattern is not received, however, the redundance circuit recognizes this fact and switches to the other communications channel. The receiving means on the peripheral devices detect that the special pattern is now being received in the specified character position of the second communications data stream and switch to read data from the second channel. Thus the error-checking features of more complicated and expensive systems are provided without the need for sophisticated processors on the peripheral devices.

Redundancy and buffering circuits

A solid-state telephone trunk interface circuit provides high isolation between a central office and telephone equipment. Opto-isolator transistors and a transformer are used to isolate the central office and the local equipment portions of the circuit. A switching transistor (Q4) is connected between a ring connector (3) and turned on and off via an opto-isolator transistor connected to a control connector (9). A ring detector (11) comprising a first diode bridge is connected between tip and ring connectors (2 and 3) via an opto-isolator transistor to a ring signal connector (13). First and second parallel and opposite sign line condition detectors are respectively connected between tip and ring connectors and via opto-isolator transistors to battery-reverse and battery-forward signal connectors (19 and 17). The voice circuit includes a second diode bridge connecting tip and ring connectors to a first winding of a transformer (T1). The circuit between the diode bridge and the first winding is completed by a high voltage transistor (Q3) which is turned on and off via an opto-isolator transistor connected to an off-hook connector ( 21). A second winding of the transformer is connected to first and second operational amplifiers respectively connected to voice signal input and output connectors (23 and 25). A feedback cancelling circuit is connected between the voice signal input connector and the input of the second operational amplifier for cancelling a portion of the voice signal input to the voice signal output.

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Herndon, VA, United States of America

John Ramsay