Motorola Corporation

John R Yeargain

Shih-Wei Sun

Faivel S Pintchovski

Yasunobu Kosa

James R Pfiester

Papu D Maniar

Stanley Michael Filipiak

Umesh Sharma

An improved contact structure and process for forming an improved contact structure for a semiconductor device. A metal (14) is formed on a first metal layer (12) positioned on a substrate (10) The metal (14) is a Group VIIB or Group VIII metal or metal oxide and increases the electrically conductive surface area (25) of the first metal layer (12). In one embodiment, a Group VIIB or Group VIII metal layer is deposited onto the first metal layer and the Group VIIB or Group VIII metal layer is anisotropically etched to form sidewall spacers (24). An insulating layer (16) is deposited overlying the first conductive layer (12) and the sidewall spacers (24). A via opening (18) is formed in the insulation layer (16) to expose a portion of the electrically conductive surface area (25). A second metal layer (22) fills the opening (18) and forms a metallurgical contact to the first metal layer (12).

Method of making a contact structure

A nonvolatile memory device includes a floating-gate electrode (14) overlying a surface (24) of a substrate (10). A diffusion barrier layer (34) extends from the substrate surface (24) along a wall surface (30) of the floating-gate electrode (14) to an upper surface (32) of the floating-gate electrode (14) and overlies the upper surface (32). The diffusion barrier layer (34) blocks the silicidation of the floating-gate electrode (14) and prevents ionic contaminants from diffusing to the floating-gate electrode (14). A charge control region (42) of the floating-gate electrode (14) is capacitively coupled to a well region (40) within the substrate (10). The well region (40) functions as a diffused control-gate electrode and regulates the voltage of the floating-gate electrode (14).

Process for fabricating a semiconductor device including a nonvolatile

A shielding structure (10) and method of formation. The shielding structure (10) has a substrate (12). A first dielectric layer (14) overlies the substrate (12). A conductive layer (16) is formed overlying the dielectric layer (14), is patterned, and is etched to form electrically isolated conductive regions from conductive layer (16). The electrically isolated conductive regions have sidewalls and the etching of conductive layer (16) exposes portions of dielectric layer (14). The exposed portions of dielectric layer (14) are etched to form trenched portions of dielectric layer (14). A second dielectric layer (18) is formed overlying the electrically isolated conductive regions, including the sidewalls, and overlying the trenched portions to create recessed regions that separate the electrically isolated conductive regions. A shielding conductive layer (20) is formed overlying dielectric layer (18) and at least partially fills the recessed regions to shield the electrically isolated conductive regions from each another.

Structure for shielding conductors

Process for forming a structure which electrically shields conductors

A process for fabricating an improved semiconductor device is disclosed wherein a protective layer of Al.sub.2 O.sub.3 is selectively formed to encapsulate a refractory-metal conductor. To form the Al.sub.2 O.sub.3 layer, first an Al/refractory-metal alloy is selectively formed on the surface of the refractory-metal conductor, then the Al/refractory-metal alloy is reacted with O.sub.2. The resulting Al.sub.2 O.sub.3 encapsulation layer acts as an O.sub.2 diffusion barrier preventing the oxidation of the refractory-metal during subsequent process steps used to fabricate the semiconductor device. In addition, the Al.sub.2 O.sub.3 layer improves the mechanical compatibility of the refractory-metal conductor with other materials used to construct the semiconductor device, such as, for example, improving the adhesion of an overlying layer of passivation glass to the refractory-metal conductor.

Process for the selective encapsulation of an electrically conductive

A salicided twin-tub CMOS process using germanium implantation to retard the diffusion of the dopants, such as phosphorus and boron. Implantation of n+ and p+ dopants after titanium salicidation is employed to fabricate devices with low junction leakage and good short-channel effects. Also, the germanium dopant may be introduced before or after the formation of the refractory metal silicide formation, and may be implanted independently or together with the dopant whose diffusion in the silicon it will modify. The employment of germanium permits the use of a phosphorus implant through a relatively thick refractory metal silicide contact layer. If arsenic is implanted through the silicide layer to solve the deep junction problem, the silicide layer must be thin to permit the passage of the larger arsenic atoms typically stopped by the silicide. Thinner silicide layers have the disadvantage of higher sheet resistances.

Growing community of inventors

Austin, TX, United States of America

John R Yeargain