Hewlett-packard Development Company, L.p.

John R Spencer

Zhubiao Zhu

Eugene Dvoskin

Garland Lee

Hong Jiang

Shane Ward

Kenneth Koch, Ii

Joel Pierre Lefebvre

Sam Babb

Michael A Buckley

Electronic circuits and methods are provided for power conservation applications. A latching relay includes a controlled switch electrically coupled within a power supply of a computer or other load. Circuitry of the present teachings controls operation of the latching relay. Set and reset conditions of the latching relay establish normal and deep standby operating modes for the computer, respectively. Manual switching or automated signaling are used to assert the set and reset relay conditions. Very low power consumption is achieved during the deep standby mode of operation.

Latching relay control circuitry

Electronic circuitry and methods are provided. Electrical energy is coupled to a transformer by way of line filter of a power supply. A clipper circuit limits the alternating-current voltage applied to the primary side. A voltage tripler receives output from the secondary side of the transformer and a resulting voltage is coupled to a voltage regulator. At least one regulated direct-current voltage is output to a load and is maintained while a current pulse is applied to a predetermined device. The electronic circuitry conforms to pending power conservation requirements for computers and other equipment.

Power supply having low quiescent consumption

Computer system powered-off state auxiliary power rail control. At least some of the illustrative embodiments are systems configured to have: a first powered-off state in which the main output power signal is deactivated within the power supply and the auxiliary power output signal is active and coupled to an auxiliary power rail of the printed circuit board; and a second powered-off state in which the main power output signal is deactivated and the auxiliary power output signal is active and decoupled from the auxiliary power rail of the printed circuit board.

Computer system powered-off state auxiliary power rail control

Dissipating power from a power supply. At least some of the illustrative embodiments are motherboards including a printed circuit board configured to couple to a main processor (and the printed circuit board configured to couple to a main power signal and an auxiliary power signal of a power supply), and a power dissipation circuit on the printed circuit board. The power dissipation circuit is configured to detect that the main power signal has powered-off, and responsive to the detection dissipate power from the auxiliary power signal for a predetermined amount of time less than an amount of time needed to fully discharge the auxiliary power signal in the absence of alternating current (AC) power to the power supply.

Method and system of dissipating power from a power supply

Regulating voltages. At least some of the illustrative embodiments are systems including a switching circuit configured to produce an intermediate voltage signal from an input voltage signal, and a first voltage regulator coupled the switching circuit and configured to produce a first regulated voltage signal from the intermediate voltage signal. The switching circuit is configured to create the intermediate voltage signal based on a switching signal having a duty cycle, and wherein the duty cycle of the switching signal is open-loop with respect the intermediate voltage signal and the first regulated voltage signal.

Method and system of regulating voltages

A configurable metal register of an integrated circuit that allows a register output value to be changed by changing any metal or any contact within a metal pattern solution of the register. More than one metal and/or corresponding contact within the metal pattern solution may be changed so that the register output value is correspondingly changed.

Method and apparatus for a configurable metal register

An apparatus and method for increasing the performance of a common-clock data bus is provided by borrowing time from the common-clock domain timing. The time may be borrowed by dynamically delaying the common-clock before providing it to a receiving path. In a system comprising a plurality of logic devices electrically coupled to a data bus, time may be borrowed from the internal common-clock timing domain of one of the plurality of logic devices when receiving data through the data bus from an external logic device. To prevent race conditions, a logic device of the plurality of logic devices may be configured to switch off the time borrowing when receiving data from an internal driving path. To avoid glitches, the logic device may be configured to switch the time borrowing feature on and off only at select time intervals.

Growing community of inventors

Fort Collins, CO, United States of America

John R Spencer