Rockwell International Corporation

Conexant Systems, Inc.

Mindspeed Technologies, Inc.

Other

John R Spence

Moataz A Mohamed

Chien-Wei Li

Rajiv Gupta

Kevin William Glass

Kevin Bowles

Michael M Yamamura

Bruce W Kinney, Jr

Mingming Zhang

Kenneth W Malich

William W Decker

Lester J Pastuszyn

Ming M Zhang

In one exemplary embodiment, the disclosed VLIW processor comprises a number of threads where each thread includes a processing unit. For example, there can be two threads, where each of the two threads has its own processing unit. According to this exemplary embodiment, a number of VLIW packets are divided into a number of issue groups. As an example, two VLIW packets are divided into two issue groups each. The first issue group in the first VLIW packet is provided to a first thread for execution in the first thread processing unit during a first clock cycle. Concurrently, the first issue group in the second VLIW packet is provided to a second thread for execution in the second thread processing unit during the same clock cycle, i.e. during the first clock cycle. Moreover, the second issue group in the first VLIW packet is provided to the first thread for execution in the first thread processing unit during a second clock cycle. Concurrently, the second issue group in the second VLIW packet is provided to the second thread for execution in the second thread processing unit during the same clock cycle, i.e. during the second clock cycle. In this manner, various resources of the VLIW processor are efficiently utilized and two VLIW packets are executed during two clock cycles. As such, the processing speed of the VLIW processor is doubled without a significant increase in the power consumed by the VLIW processor.

Apparatus and method for an improved performance VLIW processor

In one embodiment, move buses utilized in presently known VLIW processors are eliminated and replaced with a busing scheme which results in transfer of operands from each register file bank to any data path block while also reducing the total bus width and total power consumption associated with transport of operands from register file banks to data path blocks. According to this busing scheme, the speed of VLIW processor is also improved since the need for one clock cycle to move operands from one register file bank to another is overcome. In another embodiment, a scheduling restriction is used to eliminate the need for the presently required write back buses used by various data path blocks. In yet another embodiment, a scheduling restriction is imposed which results in a reduction of the number of ports, a reduction in the width of buses, and a reduction of power consumption.

Area and power efficient VLIW processor with improved speed

An apparatus and method for issue grouping of instructions in a VLIW processor is disclosed. There can be one, two, or three issue groups (but no greater than three issue groups) in each VLIW packet. In one embodiment, a template in the VLIW packet comprises two issue group end markers where each issue group end marker comprises three bits. The three bits in the first issue group end marker identifies the instruction which is the last instruction in the first issue group. Likewise, the three bits in the second issue group end marker identifies the instruction which is the last instruction in the second issue group. Any instructions in the VLIW packet falling outside the two expressly defined first and second issue groups are placed in a third issue group. As such, three issue groups can be identified by use of the two issue group end markers. In one embodiment, the template of the VLIW packet includes a chaining bit. The chaining bit is used to &ldquo;chain&rdquo; instructions appearing after the last instruction of the last issue group of a first VLIW packet to the instructions in the first issue group of a second VLIW packet. In one embodiment, a mask generation logic along with other logic blocks are utilized to generate an appropriate mask. The generated mask is used to pass through instructions in a VLIW packet which belong to a same issue group for execution in a same clock cycle.

Apparatus and method for issue grouping of instructions in a VLIW processor

A low power instruction cache is disclosed. There are a number of tag memory banks. Each tag memory bank is associated with a unique instruction cache. Each tag memory bank has a number of tag memory rows and each tag memory row has a number of tag memory cells. Certain upper bits of a program counter are compared to a tag stored in one row of a tag memory bank. If there is a match between the certain upper bits of the program counter and the tag, a hit signal is generated. The hit signal indicates that the tag memory bank containing the matched row (i.e. the matched tag) is associated with the instruction cache having a desired instruction. The desired instruction is then read from the instruction cache associated with the tag memory bank corresponding to the generated hit signal. Thus, instead of reading one instruction from each of the instruction caches and then eliminating all but one of the read instructions, only the desired instruction from a single instruction cache is read. As such, a large amount of power is saved.

Low power instruction cache

The present invention provides an efficient method of forwarding and sharing information between functional units and register files in an effort to execute instructions. A digital signal processor includes a plurality of register blocks for storing data operands coupled to a plurality of data path units for executing instructions. Preferably, each register block is coupled to at least two data path units. In addition, the processor preferably has a plurality of forwarding paths which forward information from one data path unit to another. A scheduler efficiently forwards instructions to data path units based on information regarding the configuration of the processor and any restrictions which might be imposed on the scheduler.

Processor containing data path units with forwarding paths between two data path units and a unique configuration or register blocks

The invention's reference precharge circuit and bit line precharge circuits are comprised of two NFET transistors and one PFET transistor. In the preferred embodiment of the invention where the supply voltage is 3.0 volts, the two NFET transistors result in a voltage drop of 2.0 volts so as to produce a reference precharge signal or a bit line precharge signal having a voltage of 1.0 volts. When a precharge enable signal is on, the PFET transistor is connected to ground and is barely on such that the path from the reference precharge signal or the bit line precharge signal to ground is a low impedance path. Moreover, the path from the reference precharge signal or the bit line precharge signal to the supply voltage is also of low impedance. Accordingly, the voltages present at the reference precharge signal or the bit line precharge signal are substantially noise free. The invention also utilizes a unique sense amp that quickly detects changes in the voltage level of a bit line in relation to the voltage level of the reference precharge signal. The sense amp uses an NFET transistor driven by the reference precharge signal which causes the NFET transistor to barely conduct-current. This results in dramatically increasing the reaction time of the invention's sense amp. Moreover, because the invention utilizes low bit line and reference precharge voltages, the invention's sense amp is very sensitive to small changes in the bit line voltage relative to the reference precharge voltage.

High speed sensing of dual port static RAM cell

The invention's reference precharge circuit and bit line precharge circuits are comprised of two NFET transistors and one PFET transistor. In the preferred embodiment of the invention where the supply voltage is 3.0 volts, the two NFET transistors result in a voltage drop of 2.0 volts so as to produce a reference precharge signal or a bit line precharge signal having a voltage of 1.0 volts. When a precharge enable signal is on, the PFET transistor is connected to ground and is barely on such that the path from the reference precharge signal or the bit line precharge signal to ground is a low impedance path. Moreover, the path from the reference precharge signal or the bit line precharge signal to the supply voltage is also of low impedance. Accordingly, the voltages present at the reference precharge signal or the bit line precharge signal are substantially noise free. The invention also utilizes a unique sense amp that quickly detects changes in the voltage level of a bit line in relation to the voltage level of the reference precharge signal. The sense amp uses an NFET transistor driven by the reference precharge signal which causes the NFET transistor to barely conduct current. This results in dramatically increasing the reaction time of the invention's sense amp. Moreover, because the invention utilizes low bit line and reference precharge voltages, the invention's sense amp is very sensitive to small changes in the bit line voltage relative to the reference precharge voltage.

A high speed current sense amplifier useful in memory devices, which includes a current-to-voltage amplifier that is coupled to a voltage amplifier. The current-to-voltage amplifier has an input impedance that is lower than its output impedance. The voltage amplifier has an input impedance that is larger than the input impedance of the current-to-voltage amplifier. The current sense amplifier can sense the current relationship between two current inputs in about 200 pico-seconds. Embodiments of the current sense amplifier enable current sensing either near the power supply voltage or near ground, thus eliminating the need for intermediate voltages. Embodiments of the current sense amplifier draw current from the current inputs only during the 200 pico-second sensing time and does not require external latching circuitry.

High speed current sense amplifier

A low voltage driver tolerant of high voltage and suitable for driving a processor and a memory device. A first protection NFET is coupled to the drains of a series-coupled PFET and NFET forming the basic driver components. Another protection NFET is connected in series to the first NFET. This second protection NFET requires approximately 1 volt for turn on, such that a resultant 3 volts appear at the output of the complete driver assembly. When the output driver is not enabled and 5 volt inputs are being applied from the memory circuit, the two NFET protection transistors block the 5 volts from reaching the processor output driver.

Five volt tolerant protection circuit

An apparatus is disclosed for exercising a person's knee. The apparatus includes a base member that supports a person in a supine position. There are a pair of shoulder braces connected to and extending upwardly from the base member. Each shoulder brace engages a respective shoulder of the supported person. An elongate strap is interconnected to and extends between the shoulder braces. The strap extends across the back of the supported person's leg to hold the upper section of the leg, located generally above the knee, in an upright condition extending upwardly from the base member. The lower section of the leg, located generally below the knee, may be selectively lowered and raised relative to the upper section of the leg to stretch and strengthen the knee.

Therapeutic apparatus for exercising the human knee

The LOW POWER CRYSTAL OSCILLATOR shown here reduces power consumption of a Pierce oscillator which has an inverter preferably made of an NFET N0 and a PFET P0 in series. A load, preferably an NFET N1 with its gate wired to its source, is placed in parallel with a switch, preferably a PFET P1, between P0 and Vcc. A clamp, preferably a PFET P2 with its gate wired to its source, is placed in parallel with a switch, preferably an NFET N2, between N0 and ground. The switches are enabled during power-up, thereby providing quick turn-on of the oscillator. They are then disabled, thereby reducing the voltage across the crystal XTAL and consequently reducing the power consumed.

Low power crystal oscillator

An oscillator circuit provides a symmetrical signal without halving the frequency of a crystal oscillator 12. The input 14 of the crystal oscillator 12 is low pass filtered, and the output 18 of the filter 16 is differential voltage compared with the input 14 of the crystal oscillator 12. The output 22 of the differential voltage comparator 20 is symmetrical and of the same frequency as the crystal oscillator 12. The crystal oscillator 12 is preferably a Pierce oscillator.

Symmetrical clock crystal oscillator circuit

A simplified CMOS toggle flip-flop includes a flip-flop that has an input and an output, and a toggle circuit that includes an inverter having an input connected to the flip-flop output, a transfer switch connected between the inverter output and the flip-flop input, and a toggle control responsive to an input toggle signal for closing the transfer switch to connect the inverter output to the flip-flop input to transfer the inverted flip-flop output state to the flip-flop input. The transfer switch may include an NFET having its conduction path connected between the inverter output and the flip-flop input, and having a control gate. The toggle control may include a NAND gate having a first input for receiving a toggle pulse and a second input for receiving a timing pulse, and having an output. A second inverter has an input connected to the NAND gate output and an output connected to the NFET control gate of the transfer switch.

Growing community of inventors

Villa Park, CA, United States of America

John R Spence