Delco Electronics Corporation

John R Schlais

Randy A Rusch

Thomas H Simacek

Mark Ford Henderson

The present invention relates to an integrated circuit which includes complementary MOS transistors (e.g., a CMOS circuit), an EEPROM, and to a method of making the integrated circuit. The EEPROM is incorporated in the circuit in such a manner that it does not adversely affect the high performance, low voltage operation of the CMOS circuit. Also, the EEPROM is designed so that it is programmable at a low voltage which is compatible with the low voltages typically used with the CMOS circuit. The EEPROM includes a floating gate and a control gate which have a large area of overlap so as to provide a high capacitance therebetween. This provides a high ratio (e.g., about two or greater) of the floating gate to control gate capacitance divided by the floating gate to substrate capacitance to provide the EEPROM with the low voltage operation. To make the integrated circuit, standard CMOS process steps using design rules of about two microns or less are used to make the MOS transistors. Additional steps are inserted in the standard CMOS process to form the EEPROM. The additional steps are inserted in such a manner so as not to adversely affect the operating characteristics of the resulting MOS transistors. For this purpose, any additional steps for forming the EEPROM which are carried out at a temperature of greater than 900.degree. C. are done so before the gate silicon dioxide layer of the MOS transistors is formed, and any further steps for forming the EEPROM are carried out at temperatures no greater than 900.degree. C.

Method of manufacturing CMOS integrated circuit with EEPROM

A p-channel depletion device in a MOSFET is formed and preferably comprises a silicon substrate, an N-well region, P+ source and drain regions, and a polysilicon gate which has been appropriately doped to be of a P- conductivity type. The resulting structure performs analogously to a depletion device formed in accordance with conventional methods wherein a depletion mask and implant are utilized and are characterized by a threshold voltage of approximately +250 millivolts or greater.

Method of making MOSFET depletion device

The present invention relates to an integrated circuit which includes complementary MOS transistors (e.g., a CMOS circuit), an EEPROM, and to a method of making the integrated circuit. The EEPROM is incorporated in the circuit in such a manner that it does not adversely affect the high performance, low voltage operation of the CMOS circuit. Also, the EEPROM is designed so that it is programmable at a low voltage which is compatible with the low voltages typically used with the CMOS circuit. The EEPROM includes a floating gate and a control gate which have a large area of overlap so as to provide a high capacitance therebetween. This provides a high ratio (e.g., about two or greater) of the floating gate to control gate capacitance divided by the floating gate to substrate capacitance to provide the EEPROM with the low voltage operation. To make the integrated circuit, standard CMOS process steps using design rules of about two microns or less are used to make the MOS transistors. Additional steps are inserted in the standard CMOS process to form the EEPROM. The additional steps are inserted in such a manner so as not to adversely affect the operating characteristics of the resulting MOS transistors. For this purpose, any additional steps for forming the EEPROM which are carried out at a temperature of greater than 900.degree. C. are done so before the gate silicon dioxide layer of the MOS transistors is formed, and any further steps of forming the EEPROM are carried out at temperatures no greater than 900.degree. C.

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Kokomo, IN, United States of America

John R Schlais