International Business Machines Corporation

John R Rawlins

Yuen H Chan

Antonio R Pelella

Jatinder K Wadhwa

Timothy J Charest

Carlos G Rivadeneira

Rajiv V Joshi

Otto M Wagner

Arthur D Tuminaro

Miles G Canada

Michael Nicewicz

Anuj Kohli

A late select circuit topology has pseudo-static circuits that provide fast dynamic circuit operation without the use of dynamic clock timing signals. An output from a selected set is enabled by the conjunction of bit line pulse and set select signal.

Cache late select circuit

A SRAM sense amplifier timing circuit provides various delay settings for the sense amplifier enable signal (sae) and the sense amplifier reset signal (rse) in order to allow critical timing adjustments to be made for early mode, late mode conditions by varying the timing or with of the sense amplifier output pulse. These timing adjustments are programmable using scan in bits.

Programmable sense amplifier timing generator

A sense amplifier for a memory device comprising: a first sensing stage comprising a first sensing device and a second sensing device operably connected to a first sense line and a second sense line respectively, to reduce the capacitive load on the first sense line and second sense line. A source terminal of the sensing device is connected to a switchable current sink with drain terminal thereof connected to an input of a second sensing stage. The sense amplifier also includes a second sensing stage comprising cross-coupled inverters responsive to the first sensing stage, the second sensing stage is activated by a sense enable signal following a selected delay, and an output driver responsive to the second sensing stage.

High performance dual-stage sense amplifier circuit

A high performance CMOS comparator circuit is integrated with a bypass function allowing comparing first and second data sets (A & B) with a high data width (more than 30 and illustrated as 48 bits). In many cases, it is often required to compare not only sets A&B but also set A with an additional bypass set, and the preferred circuit embodiment permits this to be achieved.

High performance CMOS pseudo dynamic bit comparator with bypass function

A chip can be provide with circuits to electrically read, blow and latch fuses. The circuit allows use of existing I/O pads used for other functions on a chip to drastically reduce the number of I/O required to blow fuses. The circuits also share critical high current carrying lines with no impact on fuse functionality and device reliability. By offering of complex fuse operations such as electrical override, even after they had been blown, essential for product screening and product diagnostics. The circuit provides a fuse blow circuit fed by a fuse sense circuit and fuse latch circuit. Stored addresses in an address buffer addresses the fuses with two sets of inputs: one providing electrical override and/or fuse blow information; and the second one, normal fuse status. Fuse integrity before and after blow is maximized with a dual voltage source drive and low current sensing.

Fuse blow circuit

A power down circuit for a default detection circuit, for detecting defects in memory array cells, comprising means for diverting the memory array standby current around the memory array cells to achieve the maximum ratio of change in input voltage as compared to the change in cell standby current and to provide improved tracking of the memory array over statistical variations of temperature, power supplies, process and other variables.

Growing community of inventors

New Paltz, NY, United States of America

John R Rawlins