Integrated Device Technology, Inc.

Step Engineering

John R Mick

Michael J Miller

Mark W Baumann

Jeff D Smith

Danh Le Ngoc

Craig Lindahl

Darrell L Wilburn

Chuen-Der Lien

Chau-Chin Wu

Yongdong Zhao

David J Pilling

Andy Peng-Pui Chan

Raymond M Chu

Thomas Diede

Robert W Stodieck

Yong-Dong Zhao

Chris Schott

Fulam Au

A matrixed memory array device is disclosed that includes input ports and output ports. Each input port is coupled to a first data bus and each output port is coupled to a second data bus that is different and separate from the first data bus. A memory brick is placed at each cross-point between first data buses and second data buses so as to switchably couple frames of data from input ports to output ports. Each memory brick contains a plurality of eight transistor (8-T) memory cells that can be used to store, erase, read, write, and switchably couple a data bit from the input port to a corresponding output port.

Apparatus and method for matrix memory switching element

A memory system includes a memory, an input circuit and a logic circuit. The input circuit is coupled to receive a memory address and, during a write operation, the corresponding write data to be written into the SRAM. The logic circuit causes the write data to be stored in the input circuit for the duration of any sequential read operations immediately following the write operation and then to be read into the memory during subsequent write operation. During the read operation, data which is stored in the write data storage registers prior to being read into the memory can be read out from the memory system should the address of one or more read operations equal the address of the data to be written into the memory while temporarily stored in the write data storage registers. Thus, no &ldquo;bus turnaround&rdquo; down time is experienced by the system thereby increasing the bandwidth of the system. The system can operate in a single pipeline mode or a dual pipeline mode.

Fully synchronous pipelined RAM

Content addressable memory (CAM) devices include CAM arrays that can identify a best match(es) from a plurality of matches when an operation to compare data applied to a CAM array against data entries within the CAM array is performed. This best match identification operation is preferably performed internal to the CAM array. The best match identification operation does not require operations to determine a highest priority match based on the relative physical locations of multiple matching entries that might be identified within the CAM array during a compare operation. The CAM device also does not require that the CAM array(s) therein be sectored into groups of entry locations (e.g., rows) having ordered priorities or that each CAM array within a multi-array CAM device be treated as a respective sector. Entries having identical priority may be entries having the same number of actively masked bits therein.

Content addressable memory (CAM) devices that can identify highest priority matches in non-sectored CAM arrays and methods of operating same

A memory system including a memory array, an input circuit and a logic circuit is presented. The input circuit is coupled to receive a memory address and a set of individual write controls for each byte of data word. During a write operation, the input circuit also receives the corresponding write data to be written into the SRAM. The logic circuit causes the write data and write control information to be stored in the input circuit for the duration of any sequential read operations immediately following the write operation and then to be read into memory during a subsequent write operation. During the read operation, data which is stored in the write data storage registers prior to being read into the memory can be read out from the memory system should the address of one or more read operations equal the address of the data to be written into the memory while temporarily stored in the write data storage registers. The logic circuit also detects which bytes of data are not to be written into the SRAM so that, during a read operation, those bytes not to be written into the SRAM are read from the SRAM in order to output a complete word corresponding to the value at the read address. No &ldquo;bus turnaround&rdquo; down time is experienced by the system thereby increasing the bandwidth of the system. The system can operate in a single pipeline mode or a dual pipeline mode.

Separate byte control on fully synchronous pipelined SRAM

A content addressable memory with programmable priority weighting and low cost match detection is described. A CAM array provides match and no-match indications of an input data word to a weight array. The weight array generates a forced match with an assigned weight that is lower than those assigned to match and no-match indications received from the CAM array. The weight array determines a winning match among the received match indications and the forced match according to their assigned weights, and provides an indication of the winning match to an encoder. The encoder provides an address of the winning match, and a match detect output which is generated from the success or lack thereof of the forced match being determined the winning match.

Content addressable memory with programmable priority weighting and low cost match detection

A content addressable memory (CAM) system that includes first and second CAM arrays, which generate first and second sets of match control signals, respectively, having higher and lower priorities, respectively. The first CAM array is enabled during a first memory cycle, and the first set of match control signals are analyzed. If a match exists in the first CAM array, a first priority encoder is enabled to process the first set of match control signals. If no match exists, the first priority encoder is not enabled, and a second memory cycle is initiated. The second CAM array is enabled during the second memory cycle, and the second set of signals is analyzed. If a match exists in the second CAM array, a second priority encoder is enabled to process the second set of match control signals. If no match exists, the second priority encoder is not enabled.

Pipelining a content addressable memory cell array for low-power operation

A CAM system is provided for determining which data word in a CAM array exhibits the longest continuous, unmasked match with an input data value. The input data value is divided into non-overlapping subfields, thereby creating a series of keys, the first key of the series including either the least significant bit (LSB) or most significant bit (MSB) of the input data value. The CAM array is divided along columns into a similar series of non-overlapping sub-arrays corresponding to the subfields defined by the series of keys. A first CAM sub-array compares the first key with its stored rows of data bit values to generate a first match signal. The first match signal disables each row of the second CAM sub-array for which the corresponding row of the first CAM sub-array did not show a match. A second CAM sub-array then compares the second key with its enabled rows to generate a second match signal. The second match signal disables each row of the third CAM sub-array for which the corresponding row of either the first or second CAM sub-array did not show a match. This comparison process continues in sequence with the remaining keys and CAM sub-arrays. The row of the CAM array that shows a match over the most consecutive comparison operations contains the longest match for the input data value. If multiple rows match over the same number of comparison operations, a priority encoder determines which location has the highest priority.

Content addressable memory with longest match detect

Fully synchronous pipelined ram

A memory device (,) having left (,) and right (,) ports for communicating with left (,) and right (,) electronic devices, includes memory banks (,-,-,), semaphore logic (,), and port coupling circuitry (,-,-,-,-,-,-,). The semaphore logic generates bank access grant signals (,) on a first received basis in response to bank access requests from the left and right electronic devices, and the port coupling circuitry couples selected memory banks to the left and right ports in response to the bank access grant signals. Also included in the memory device are mail-box registers (,-,L&tilde;,-,L,,-,R&tilde;,-,R), interrupt generating circuitry (,-,L&tilde;,-,L,,-,R&tilde;,-,R,,), and interrupt status and cause registers (,L&tilde;,L,,R&tilde;,R,,L&tilde;,L,,R&tilde;,R). The left and right electronic devices use the mail-box registers to send messages to each other without waiting. The interrupt generating circuitry generates interrupts to notify the left and right electronic devices when their bank access requests have been granted, and when a message has been written into one of the mail-box registers for them. The interrupt status and cause registers provide information as to which memory banks the left and right electronic devices have been granted access to, and which mail-box registers contain messages for them.

Multi-ported memory architecture using single-ported RAM

A memory system including a memory array, an input circuit and a logic circuit is presented. The input circuit is coupled to receive a memory address and a set of individual write controls for each byte of data word. During a write operation, the input circuit also receives the corresponding write data to be written into the SRAM. The logic circuit causes the write data and write control information to be stored in the input circuit for the duration of any sequential read operations immediately following the write operation and then to be read into memory during a subsequent write operation. During the read operation, data which is stored in the write data storage registers prior to being read into the memory can be read out from the memory system should the address of one or more read operations equal the address of the data to be written into the memory while temporarily stored in the write data storage registers.

A memory device (201) having left (203) and right (204) ports for communicating with left (205) and right (206) electronic devices, includes memory banks (401-0.about.401-7), semaphore logic (302), and port coupling circuitry (403, 404, 405-0.about.405-7, 406-0.about.406-7, 407-0.about.407-7). The semaphore logic generates bank access grant signals (313, 314) on a first received basis in response to bank access requests from the left and right electronic devices, and the port coupling circuitry couples selected memory banks to the left and right ports in response to the bank access grant signals. Also included in the memory device are mail-box registers (2500-0L.about.2500-3L, 2500-0R.about.2500-3R), interrupt generating circuitry (2514-0L.about.2514-3L, 2514-0R.about.2514-3R, 2900, 3000, 307, 308), and interrupt status and cause registers (3101L.about.3102L, 3101R.about.3102R, 3301L.about.3302L, 3301R.about.3302R). The left and right electronic devices use the mail-box registers to send messages to each other without waiting. The interrupt generating circuitry generates interrupts to notify the left and right electronic devices when their bank access requests have been granted, and when a message has been written into one of the mail-box registers for them. The interrupt status and cause registers provide information as to which memory banks the left and right electronic devices have been granted access to, and which mail-box registers contain messages for them.

Semaphore enhancement to allow bank selection of a shared resource

A memory system includes a memory, an input circuit and a logic circuit. The input circuit is coupled to receive a memory address and, during a write operation, the corresponding write data to be written into the SRAM. The logic circuit causes the write data to be stored in the input circuit for the duration of any sequential read operations immediately following the write operation and then to be read into the memory during subsequent write operation. During the read operation, data which is stored in the write data is storage registers prior to being read into the memory can be read out from the memory system should the address of one or more read operations equal the address of the data to be written into the memory while temporarily stored in the write data storage registers. Thus, no 'bus turnaround' down time is experienced by the system thereby increasing the bandwidth of the system. The system can operate in a single pipeline mode or a dual pipeline mode.

A memory system including a memory array, an input circuit and a logic circuit is presented. The input circuit is coupled to receive a memory address and a set of individual write controls for each byte of data word. During a write operation, the input circuit also receives the corresponding write data to be written into the SRAM. The logic circuit causes the write data and write control information to be stored in the input circuit for the duration of any sequential read operations immediately following the write operation and then to be read into memory during a subsequent write operation. During the read operation, data which is stored in the write data storage registers prior to being read into the memory can be read out from the memory system should the address of one or more read operations equal the address of the data to be written into the memory while temporarily stored in the write data storage registers. The logic circuit also detects which bytes of data are not to be written into the SRAM so that, during a read operation, those bytes not to be written into the SRAM are read from the SRAM in order to output a complete word corresponding to the value at the read address.

A burst address sequencer and method for providing sequential addresses to a memory which operates in response to a clock signal. The burst address sequencer includes a plurality of two-stage address registers, with an address register being provided for each address bit. Prior to an initial rising edge of the clock signal, an initial address is loaded into the first stages of the two-stage address registers. In response to the initial rising edge of the clock signal, the initial address is clocked through the second stages of the two-stage address registers, directly to the memory. Subsequent addresses are derived from the initial address by circuitry within the burst address sequencer. These subsequent burst addresses are provided to the first stages of the addresses registers prior to subsequent rising edges of the clock signal and clocked out to the memory in response to these subsequent rising edges of the clock signal. By providing the addresses directly from the second stage of the address registers to the memory, the logic gate delay associated with providing the addresses to the memory in response to the rising edge of the clock signal is minimized.

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San Jose, CA, United States of America

John R Mick