Data General Corporation

John R McDaniel

Louis A Lemone

Salvatore Faletra

Steve A Caldara

Stephen A Caldara

Joseph P DeYesso

Edward Gershenson

Mark C Lippitt

Kenneth S Goekjian

David M Harrington

Kenneth R Andrews, Jr

Paul Funk

John E Shur

Donald J Barbarits

Lou Lemone

Paul F Joseph

A data processing system is disclosed in which a plurality of high performance, intelligent, mass storage input-output devices are linked to a host controller by an input-output interface bus which is divided into three sections. Each section is completely independent of the other two sections and used for a different and specific purpose. One section is used to transfer commands and retrieve status information. A second section is used to handle device requests for data transfer and device signals for operation complete. The third section is used to transfer data to and from a device. Since the three sections are completely independent, simultaneous transfer of command control and data to different input-output devices or to a single input-output device can be performed.

Interface bus with independent data, command and direct control sections

A data processing system which includes a host processor and an input/output (I/O) controller unit for controlling communication with I/O devices. The controller processor receives I/O commands from the host processor, accesses and stores control block lists of control commands associated with such I/O commands, and executes the control commands from such control block lists. The controller unit stores controller information concerning the operational capability of the controller unit and the host processor is capable of accessing such controller information and in turn can modify such operational capability if desired.

I/O controller for controlling the sequencing of execution of I/O

Logic circuitry for use in electrical apparatus for providing an interrupt signal to a controller when there is a power failure in the electrical apparatus. The logic circuitry is connected to a bus from the controller. When the logic circuitry receives a power failure signal, it sets an interrupt state register and provides an interrupt signal on the bus as long as the interrupt state register is set. If the power failure signal no longer indicates a power failure, the logic circuitry responds to a signal from the controller indicating that the interrupt has been received by resetting the interrupt state register, thereby ending the interrupt. However, if the power failure signal is still active, the logic circuitry will not reset the interrupt state register in response to the signal from the controller. The logic circuitry is incorporated into a system having a plurality of individual electrical apparatuses, each of which is capable of generating an interrupt signal when it detects a power failure in itself, and a plurality of controllers, each controller having an associated bus connected to each individual apparatus such that the system can be configured to allow any selected one of said controllers to be connected to and control any selected one of said apparatuses. The logic circuitry receives the power failure signal from the selected apparatus, provides the interrupt signal to the appropriate controller and resets the interrupt state register under control of the controller if the power failure signal from the selected apparatus is no longer present.

Apparatus for providing an interrupt signal in response to a permanent

The disclosure relates to a memory mapping system wherein information is stored on a page by page basis in memory in discontiguous locations therein with the address of the next page in which storage is to take place always being available in the controller to minimize delay in storage from the end of one page to the beginning of the following page, regardless of page location in memory. When a user makes a request for storage space in memory, the amount of memory required is determined and the host looks to see where it can obtain that memory. Typically, use of discontiguous memory locations is required. All of the information relative to the addresses of the discontiguous storage locations in memory is provided to the controller by the host computer in a single command rather than after each move to a discontiguous storage location. All jumps to discontiguous storage locations are then performed independent of the host computer.

Memory mapping system

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Acton, MA, United States of America

John R McDaniel