Trw Limited

Farallon Computing Corporation

John R Marum

Harold H Webber, Jr

George W McIver

James B Cho

The present invention provides automatic configuration of the transmit and receive paths of a network connection, preferably a 10Base-T network connection. It senses which pair in a cable is used for TX signals and which is used for RX signals, then it automatically swaps or unswaps the RX and TX pairs of the port so that a connection is made regardless of whether a crossover or straight-through cable is used. The invention uses link integrity pulses, which are used to periodically test the integrity of the network, to determine which pair is for reception and which is for transmission. Since the auto-crossover transceiver has line receivers and line drivers connected to both pairs of the cable, once it determines which pair is TX and which is RX, it selects the appropriate line receiver and driver to match the cable configuration. The present invention allows connection to a network where another node on the network is either of the standard 'hub' type, of the standard 'MAU' type, or of the auto-crossover type.

Method and apparatus for automatic configuration of a network connection

The present invention provides a method and apparatus for extending an Ethernet 10Base-T local area network topology from only allowing point-to-point link segments to allowing daisy-chained segments having multiple nodes on each segment. Thus, computer equipment can be connected in a bus topology while retaining the characteristics of a 10Base-T node according to IEEE Standard 802.3 for 10Base-T Ethernet. In the preferred embodiment of the present invention, a non-reclocking repeater at a 10Base-T node retransmits data packets from the node to subsequent nodes in a daisy-chained segment. When the repeater is not powered, bypass circuitry connects the two ends of 10Base-T wiring to remove the inactive node from the daisy-chain segment. The repeater includes modular connectors and analog transmit and receive sections for transmitting and receiving differential signals between two network link interfaces and an AUI. The repeater further comprises digital logic to implement the functional circuitry of a 10Base-T Medium Attachment Unit (MAU). It includes logic to detect data packets having two formats and link pulses. Because the IEEE Standard 802.3 only allows a fixed number of bits to be lost at a 10Base-T node, a repeater retransmits data packets having formats such that nodes further down the segment do not lose additional bits. The present invention also includes diagnostic circuitry including LEDs to aid installation and to provide useful information including collision detection and link integrity.

Method and apparatus for connecting nodes for a computer network

An Ethernet adapter card for automatically switching a workstation into a network is provided. The adapter card utilizes a current circuit to sense current drawn by an external communications network and a circuit for automatically switching between a card-mounted internal transceiver and the network's external transceiver whenever the external network is coupled to the workstation via an AUI port. The adapter card provides for default selection of the internal transceiver when the external communication network is disconnected from the workstation AUI port.

Ethernet automatic adapter interface card

A fault tolerant register employing triple redundant storage of data and continuous voting to protect the data from Single Event Upset, or SEU. The fault tolerant register includes a single master multiplexer, three slave multiplexers connected in parallel to the output of the master multiplexer and three voting circuits positioned in feedback paths of the slave multiplexers. The slave multiplexers provide triple redundant storage for the data and the voting circuits correct any data that might become disrupted. The fault tolerant register of the present invention provides greatly improved SEU tolerance without a large increase in circuit area or without resorting to error correction and its attendant scrubbing process.

Triple redundant fault-tolerant register

Switching circuitry for automatically connecting two sets of terminals in two circuit modules, through a larger set of conductors, some of which may be defective or unavailable for other reasons. The circuitry includes two identical switching matrices, each of which receives signals indicative of the availability status of the conductors, and connects the terminals to an available subset of the conductors. Each switching matrix has an array of switching cells arranged in such a manner that a cell will connect a terminal to a conductor unless the conductor is not available, or unless the same terminal has already been assigned to another conductor, or the same conductor has already been assigned to another terminal.

Redundancy interconnection circuitry

An electronic system having multiple identical subsystems, some of which can be excluded from the system when defective or held as spares. A mapping circuit associated with each subsystem has a first register for storing a physical address of the subsystem and a second register for storing a logical address. To configure the system to include a selection of subsystems, pairs of physical and corresponding logical addresses are transmitted to the subsystem mapping circuits. When a transmitted physical address matches the address stored in the first register, the second register is enabled to receive a transmitted logical address. The mapping of physical to logical address is therefore distributed among all of the subsystems rather than being handled in a central mapping unit. Subsystems that are to remain out of service have a null address stored in their second registers. In normal operation of the entire system, a logical address transmitted to the subsystems is compared with the logical address stored in each second register, and only the matching subsystem is selected for operation.

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Berkeley, CA, United States of America

John R Marum