Lsi Logic Corporation

Lsi Corporation

Avago Technologies General IP (singapore) Pte. Ltd.

Symbios Logic Inc.

Symbios, Inc.

John R Kloeppner

Dennis E Gates

Keith W Holt

Bret S Weber

Mohamad H El-Batal

Rodney A DeKoning

Russell J Henry

Robert E Stubbs

Jason M Stuhlsatz

Donald Roman Humlicek

Randolph Wesley Sterns

Charles E Nichols

Jeremy D Stover

Curtis W Rink

Randy Kay Hall

Macen Shinsato

Grover G Phillips

Apparatus and circuitry are provided for supporting collection and/or verification of data integrity information. A circuitry in a storage controller is provided for creating and/or verifying a Data Integrity Block ('DIB'). The circuitry comprises a processor interface for coupling with the processor of the storage controller. The circuitry also comprises a memory interface for coupling with a cache memory of the storage controller. By reading a plurality of Data Integrity Fields ('DIFs') from the cache memory through the memory interface based on information received from the processor, the DIB is created in that each DIF in the DIB corresponds to a respective data block.

Apparatus and circuitry for memory-based collection and verification of data integrity information

Apparatus and systems for improved access to storage devices from the sides of sleds mounted in storage enclosures. Embodiments provide apparatus and systems for a sled in a storage enclosure that provides access to storage devices on either side of the sled when the sled is slid forward out of its enclosure. Multiple sleds may be enclosed within a single enclosure to permit access to a portion of the storage devices in the enclosure hence reducing the problems of instability of the rack if the enclosure is mounted near the top of the rack.

Apparatus and systems having storage devices in a side accessible drive sled

Methods and apparatus for improved calculation of redundancy information in RAID storage controllers. Features and aspects hereof provide for a firmware/software element (FPE) for generating redundancy information in combination with a custom logic circuit (HPE) designed to generate redundancy information. A scheduler element operable on a processor of a storage controller along with the FPE determines which of the FPE and HPE is best suited to rapidly complete a new redundancy computation operation and activates or queues the new operation for performance by the selected component.

Methods and apparatus for improved raid parity computation in a storage controller

A configurable storage array controller can be configured to either a single-processor configuration or a multi-processor configuration by configuring a data bus switch system.

Configurable storage array controller

A method for verifying the proper communication of data packets from an initiator device on a PCIe data bus to a target device on the data bus. A target-specific counter on the initiator is synchronized to an initiator-specific counter on the target with the same value. The initiator writes the value of the target-specific counter into the tag field of the packet header, and also writes an identifier of the initiator into the header. Then the initiator sends the packet to the target on the PCIe data bus. Upon receipt of the packet, the target reads the identifier and checks the value against the appropriate initiator-specific counter on the target. When the value is not equal to the initiator-specific counter on the target, then it generates an error message. An additional memory write with specific data is posted from the initiator to the target. A memory read is posted of the additional memory write location from the initiator to the target. The operation of the initiator is continued when a good status and data matching the additional write data is returned from the target, and operation is halted when an error status is returned or data that does not match the additional write data.

Posted memory write verification

Apparatus, systems and methods for clustering multiple PCI Express hierarchies to enable access of components in different hierarchies. Each PCI Express hierarchy includes a root device as well as a cluster port for coupling each hierarchy to each other hierarchy of a physical cluster through a PCI Express switched fabric. Memory addresses and transaction IDs are re-mapped by the cluster port of each hierarchy to partition the PCI Express space of the system of multiple hierarchies. A first portion of the partitioned space is reserved for access to local components within a hierarchy. A second portion of the space is used to access remote components of other hierarchies from within a different first hierarchy. The address and transaction ID values exchanged in such remote transactions are re-mapped and used by the cluster port of each hierarchy to route exchanges between hierarchies using standard PCIe root devices, endpoint devices, and switches.

Apparatus and methods for clustering multiple independent PCI express hierarchies

Systems and methods for handling I/O requests from a host system to a storage system. A system includes an I/O module for processing I/O requests from a host system, a virtualized storage element, and a communication medium coupling the I/O module to the virtualized storage elements. The virtualized storage element includes a mapping table for translating virtual storage locations into physical storage locations and a plurality of physical storage locations. The virtualized storage element generates base virtual addresses using the mapping table to communicate the base virtual addresses to the I/O module. The I/O module generates specific virtual addresses using the base virtual addresses and using information derived from the I/O requests. The I/O module uses the specific virtual addresses in communication with the virtualized storage element to identify the physical storage locations in the virtualized storage element.

Method and apparatus for handling storage requests

A hardware assisted searching mechanism is provided that offloads the processor from searching operations. In a preferred embodiment, the hardware assisted searching mechanism performs a binary search of an associated 32 bit register against a binary search table that is set up by the firmware of the storage system. From this binary search table, an index into other structures stored in firmware is obtained that may be used to identify a target device. For example, when a search is to be performed due to receipt of an I/O operation, the firmware, i.e. software instructions stored in the persistent memory chip that are executed by the system processor, writes a 32 bit value to a hardware register that is used by the hardware assisted searching mechanism of the present invention. The hardware assisted searching mechanism performs a binary search of a binary search table based on the contents of the hardware register and returns an index of the entry in another hardware register. This index is then used to index into a storage device mapping structure stored in the firmware that are indexed in the same manner as the binary search table. The index provides a starting point in the storage device mapping structure and from this starting point, the logical unit number is used to identify a particular storage array and logical unit number for the destination of the I/O operation.

Method and apparatus for performing a high speed binary search in time critical environments

Methods and associated structure for improving storage system performance by reducing latency associated with communication medium transactions internal to a storage subsystem. In one aspect of the present invention, an I/O control element associated with a storage system transmits prefetch read requests to an associated storage element of the storage system in response to receipt of a host system request. This allows the storage element to commence data transfer to the I/O element in advance of the I/O element returning the data to the host system. Subsequent transfers of data from the storage element to the I/O element then overlap the transfer of data from the I/O element to the host. In another specific aspect of the present invention, methods and associated structures eliminate latency associated with PCI-X bus split transactions between the front-end (host interface portion) of the I/O element and the back-end (storage element interface) of the I/O element by overlapping the transfer of prefetched data to the host system with continued fetching of subsequent data from the storage element.

Method and structure for read prefetch in a storage complex architecture

A shared resource manager circuit for use in conjunction with multiple processors to manage allocation and deallocation of a shared resource. The shared resource manager allocates and deallocates software resources for utilization by the processors in response to allocation and deallocation requests by the processors. The shared resource manager may include a bus arbitrator as required in a particular application for interfacing with a system bus coupled to the processors to provide mutual exclusion in access to the shared resource manager among the multiple processors. The shared resource manager may manage a memory block (FIFO queue) with multiple resource control blocks. A system may advantageously apply a plurality of shared resource managers coupled to a plurality of processors via a common interface bus. Each shared resource manager device may then be associated with management of one particular shared resource.

Shared resource manager for multiprocessor computer system

The present invention provides storage system controllers and methods of controlling storage systems therewith. The controller ( ) includes a main processor ( ), a memory ( ), a device interface ( ) adapted to interface a peripheral component ( ), such as a RAID storage device, with the storage system controller, and an operations sequencer ( ). The main processor sequences a plurality of tasks to be executed to complete an operation. The operations sequencer coordinates an execution of the plurality of tasks. Methods of the invention include receiving a task status for each of the plurality of tasks that is executed, and issuing an interrupt to the main processor after all of the plurality of tasks of the operation are finished executing. In this manner, the operations sequencer offloads at least some of the main processor overhead to improve processor efficiency.

Methods and apparatus for raid hardware sequencing to achieve a higher performance raid architecture

In one embodiment, the present invention provides a storage system controller ( ) having a main processor ( ), a memory ( ) and a device interface ( ) adapted to interface with a peripheral component ( ). The controller further includes an interrupt management scoreboard ( ) adapted to receive a plurality of writes from the peripheral component(s) prior to interrupting the main processor. The main processor identifies a group of tasks to be executed, and sets up the scoreboard to await the completion of the tasks before interrupting the main processor.

Methods and apparatus for using interrupt score boarding with intelligent peripheral device

A system and method for managing data stored in a cache block in a cache memory includes a cache block is located at a cache block address in the cache memory, and the data in the cache block corresponds to a storage location in a storage array identified by a storage location identifier. A storage processor accesses the cache block in the cache memory and provides a cache management command to a command processor. A processor memory coupled to the storage processor stores a search key based on the storage location identifier corresponding to the cache block. A command processor coupled to the storage processor receives a cache management command specified by the storage processor and transfers the storage location identifier from the processor memory. A cache management memory stores a cache management structure including the cache block address and the search key. A cache management processor is coupled to the cache management memory by a second link to manipulate the cache management structure in a hash table with linked lists at each hash queue element within the cache management memory in accordance with the cache management command and the search key.

Hardware mechanism for managing cache structures in a data storage system

Methods and associated apparatus operable in a RAID subsystem to improve the speed and flexibility of initializing the subsystem by storing configuration and identification information in a reserved area on each disk drive in the subsystem. The reserved area on each disk drive of the disk array contains a unique identifier to identify the particular disk drive from all others and further contains group configuration information regarding all groups in which the particular disk drive is a member. The configuration and identification information is generated and written to each disk drive in the disk array when the particular disk drive is configured so as to be added or deleted from groups of the subsystem. Upon subsystem reset (e.g. power on reset or other reset operations), the RAID controller in the subsystem determines the proper configuration of the RAID groups despite temporary unavailability or physical relocation of one or more disk drives in the disk array. In addition, entire groups of disk drives may be moved from one subsystem to another and automatically recognized by the new controller when the controller is reset.

Methods and structure to maintain raid configuration information on

A method for transferring data in a controller is disclosed which includes the steps of providing a processor having an internal first bus, providing a second bus, connecting a memory device to the second bus, connecting a disk drive to the second bus, transferring first data between the memory device and the processor across the first and second buses, and transferring second data between the memory device and the disk drive across the second bus. A disk array controller architecture is also disclosed.

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Buhler, KS, United States of America

John R Kloeppner