Silicon Graphics, Incorporated

Pmc-sierra, Inc.

Mips Technologies, Inc.

John R Kinsel

Thomas J Riordan

Michael DeMar Taylor

Paul S Ries

Albert M Thaik

Tom Riordan

A single memory element, which may consist of general purpose SRAM chips, implements both tag and data cache memory functions, resulting in an efficient, low cost implementation of high speed external cache memory. In one embodiment, a bank of general purpose RAM used by a microprocessor as an external cache memory stores both cache tags and cache data in separate memory locations. During a read operation, the microprocessor retrieves a cache tag from the bank of general purpose RAM before retrieving corresponding cache data therefrom, and compares the cache tag to a memory address to assess whether requested data resides in the cache memory. The comparison may also be performed concurrently by a system controller device, which may abort the main memory access if a cache hit is detected.

Cache memory architecture with system controller device that compares cache tags to memory addresses received from microprocessor

A single memory element, which may consist of general purpose SRAM chips, is used to implement both tag and data cache memory functions, resulting in an efficient, low cost implementation of high speed external cache memory. In one embodiment, a bank of general purpose random access memory used by a microprocessor as an external cache memory stores both cache tags and cache data in separate memory locations. During a read operation, the microprocessor retrieves a cache tag from the bank of general purpose random access memory before retrieving corresponding cache data therefrom, and compares the cache tag to a memory address to assess whether requested data resides within the cache memory. The microprocessor preferably accesses the bank of general purpose random access memory using a memory mapping function which maps the memory address into a cache tag address and a cache data address.

Cache memory architecture and associated microprocessor design

Techniques for matching the speed of a microprocessor to potentially slower external system components. A master clock signal is communicated to a clock generator on the processor chip. The clock generator provides at least one external clock signal, which is communicated to various portions of the system. The clock generator includes programmable clock division circuitry that allows the external clock signal to be generated at any selected one of a plurality of fractions of the master clock frequency. The data pattern (the particular cycles in a sequence during which the processor outputs a data word as part of a multiple-data-word sequence) is programmable independently of the external clock programming.

Processor chip for using an external clock to generate an internal clock

Processor chip having on-chip circuitry for generating a programmable

An error detection system wherein 64 bits of data word are protected by 8 check bits which yield 8-bit syndromes. Single-bit errors are indicated by syndromes that contain exactly three '1's or by syndromes that contain exactly five '1's in which bits 0-3 or 4-7 of the syndrome are all '1.' Single-bit errors that occur from faulty check bits are indicated by syndromes that contain exactly one '1.' All two-bit errors, and four-bit errors within a nibble, are indicated by syndromes that contain an even number of '1's (i.e., an even number of '1's). Three-bit errors within a nibble are indicated by syndromes that contain five '1's in which bits 0-3 of the syndrome and bits 4-7 of the syndrome are not all '1.' Four-bit errors within a nibble are indicated by syndromes that contain four '1's. In another embodiment of the invention, 25 bits of data word are protected by 7 check bits yielding 7-bit syndromes. Single-bit errors are indicated by syndromes that contain exactly three '1' s except single-bit errors that occur from faulty check bits are indicated by syndromes that contain exactly one '1'. Two-bit errors are indicated by syndromes that contain an even number of '1's, and three-bit errors within a nibble are indicated by syndromes that contain five '1's or seven '1's. Four-bit errors within a nibble are indicated by syndromes that contain four '1's or six '1's.

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San Jose, CA, United States of America

John R Kinsel