U.S. Philips Corporation

John R Kinghorn

Richard E Bugg

Christopher P Summers

David R Tarrant

Jeremy R Stevens

Terence A Douglas

Raymond J Fisher

A tape indexing arrangement for video recorders records the index on the tape using standard broadcast teletext codes. When a tape is inserted, the contents list it contains is written onto an index RAM in the recorder (,). When a new program is recorded, a program identification is generated from PDC or EPG data (,). At a suitable later time, the contents of the index RAM are recorded on the tape (,).

Video recorder

An arrangement for the control of viewing of a television program in which a classification code is transmitted with the video signal, for example, in an extension packet of a teletext signal, includes a decoder (23) which detects the received codes and passes them to a microcontroller (27). An authorized user is able to enter codes of permitted program classifications by means of a remote control unit (28). Codes representing these permitted classifications are stored in a non-volatile memory (29). The received and permitted codes are compared in the microcontroller (27) which inhibits the video (25) and/or audio (32) circuits if the received codes are not permitted codes. The non-volatile memory (29) is arranged to store a plurality of different program classifications, each of which is valid for different periods of the day.

Television access control system

A television receiver includes a teletext decoder having a page memory (PM) into which teletext data is read from a data acquisition circuit (DAC) via an interface circuit (MIC) under control of a microprocessor (PRO). The microprocessor is also used to control functions of the television receiver and to cause on-screen display messages to be produced. When an on-screen display message is to be produced, the microprocessor sets a bit in the memory PM which causes a latch to be set which in turn causes a multiplexer (MUX) to apply data from an auxiliary memory (APM) to a character generator (CG). When the on-screen display message is to be deleted, the bit in the page memory is reset causing the latch to be reset and the multiplexer to apply data from the page memory to the character generator. This enables on-screen display messages to be applied to the character generator without losing any of the teletext data stored in the page memory.

Combination TV receiver and teletext processor with on-screen message

A 'correct page header received' (CPHR) flip-flop (3) is set by the page header of a required teletext page and reset by the next following page header, a 'page end' flip-flop (15) generates a page end output (17) in response to the receipt of the next following page header, a 'row received' flip-flop (11) detects at least one row of the required teletext page, a gate (14) inhibits the generation of an end of page output (21) for a predetermined period, typically corresponding to three field intervals, and an AND gate (18) further inhibits the generation of an end of page output (21) if there has been a subsequent detection of a further page header of the required teletext page within the predetermined period.

Teletext decoder apparatus including feature of inhibiting generation of

In a teletext decoder, the digital codes for a requested page are acquired and stored in the page memory each time the page occurs in the recurrent teletext transmission cycle. This means that the stored digital codes are over-written in the page memory on each occurrence of the page. Where an acquired digital code has been changed for a different code in the decoder so as to display a special character, this different code has hitherto been over-written periodically by the original code, giving rise to a flicker in the display at the character position concerned. The present invention prevents this flicker by arranging the decoder to look at each stored digital code before it is over-written, and preventing the over-writing from occurring when the digital code pertains to a special character.

Teletext decoders with inhibit means for precluding over-writing codes

A teletext decoder has a character memory comprising a common language set of characters and a plurality of sub-sets of national option characters, each of which latter sets makes up a complete national language set when combined with the common language set. The totality of characters are addressable using n bit digital codes together with an additional bit which determines one of two addressing modes. In one addressing mode, only one of the national option sub-sets can be selected by addressing means so that a page can be displayed using one complete language set. In the other addressing mode, all the national option sub-sets can be selected by processor means to enable a page to be displayed using more than one language set.

Improved teletext decoder which accommodates an increased number of

A system for video recorder programming using existing television broadcast teletext transmissions. The programs required are chosen from schedules displayed on teletext pages, the necessary control information is loaded automatically into a video recorder, and program labels are transmitted to ensure that the correct programs will be recorded even if program timings are altered. All the control information for achieving the above are fitted into the coding structure of a teletext transmission using extension packets additional to data packets containg display data. The invention also extends to a video recorder with its own teletext decoder for processing the control information.

Video cassette recorder programming via teletext transmissions

A teletext decoder for full-channel operation includes a 'row-found' register in which a flag is put for each data row which is actually present in a selected teletext page that is received and stored in the page memory of the decoder. The decoder further includes control means which on read-out from the page memory allows the utilisation of only those data rows of the stored page for which there is a flag in the 'row-found' register. Because teletext pages can contain different numbers of data rows, it is normally necessary to empty the page memory before a selected new page is received and stored since otherwise data rows of a stored old page which are not over-written by corresponding data rows of the new page would be included in the data read out for the new page. The provision of a flag for each received data row of the new page and the action of the control means prevents this happening. It then becomes unnecessary to delay reception of a new page until an old page has been removed from the page memory. Means are also provided for taking account of parity errors in received character data codes.

Teletext decoders

A teletext television receiver has a character memory comprising a common language set of characters and a plurality of sets of national option characters, each of which latter sets makes up a complete national language set when combined with the common language set. The totality of characters are arranged for addressing in two different modes. In one addressing mode, only one of the national option sets can be selected for page display as determined by control bits contained in the page header, so that the page can be only in one language. In the other addressing mode, all the national option sets can be selected for page display as determined by ghost row information of an acquired page, or locally by the receiver. This allows a display page to be in more than one language. FIGS. 3 and 4 show the code tables for the two addressing modes.

Television receiver arrangements

A digital code detector circuit for detecting on a priority basis those code combinations of an n-bit binary digital code (n&gt;3) which contain only a single bit of a first binary value (e.g. the code combinations 1000, 0100, 0010 and 0001 of a 4-bit binary digital code). The circuit comprises a set of n input leads with associated inverters to supply the inverse of the input code combinations as well as the input code combinations to a logic gating arrangement. The gating arrangement drives m output circuits, where the m is the number of bits of output address code combinations corresponding to each possible input code combination of n-bits. When more than one of the input code combinations containing only a single bit of the fixed binary value are present concurrently on the set of input leads, the gating arrangement is such that only the m-bit address code for the input code combination having the higher binary value is produced by the output circuits.

Digital code detector circuits

A dynamic two-phase circuit arrangement includes two dynamic switching circuits, each of which has an input stage, a non-inverting output stage and an inverting output stage. Two-phase control of the two dynamic switching circuits is effected by two drive pulses. The arrangement also includes combinatorial logic which is operated by the drive pulses to feed counter clock pulses to the first dynamic switching circuit. The first dynamic switching circuit performs a divide-by-two operation in response to the clock pulses and drives the second dynamic switching circuit from its Q-output. The second dynamic switching circuit includes an additional switching transistor which is also driven from the Q-output of the first dynamic switching circuit. This transistor is connected to perform an OR-function with the non-inverting output stage of the second dynamic switching circuit. As a result, this output stage produces shift pulses having half the repetition frequency of the clock pulses. The duration of these shift pulses corresponds to the period of the two-phase control cycle of the arrangement.

Dynamically operable two-phase logic circuits

A data entry keyboard apparatus comprises a key-switch array (900) and associated electronic logic circuits (941). The key switches (901) of the array are so interconnected with each other and with connection terminals (902) to (905) of the logic circuits (941) that any one of these connection terminals can be interconnected with any other one by the actuation of an appropriate key-switch. The logic circuits (941) have a first set of coincidence gates (912) one for each key-switch (901). One input of each of these gates is connected to receive a particular one of a plurality of pulse signals of different phases produced by a pulse sequencer (906). A second input of each of these gates is connected to receive the same pulse signal via the key-switch array when the appertaining key-switch (901) is actuated. The coincidence or detection at an AND-gate of the same pulse signal at both inputs produces an output signal signifying actuation of the appertaining key-switch. The apparatus has n/2.times.(n-1) key switches (901) in the array, where n is the number of connection terminals. Two additional key switch sets (916 to 919) and (920 to 923) are provided in the array (900) without increasing the number of connection terminals by utilizing existing ground and clock pulse terminals to enter inputs to respective further coincidence gate sets (924 and 927) which pertain to the two additional key switch sets, respectively. Respective groups of latches (913, 914; 925,926; and 928,929), feed the gate output signals to an encoder (915) via a priority detector (936 to 939).

Data entry keyboard apparatus

Digital data apparatus comprising a processing unit which can have access to different numbers of memory units over a common data bus. The processing unit can address selectively the memory units with address codes over an address bus. An address code is valid when there is a corresponding memory unit and invalid when no memory unit is provided in respect of it. The validity of an address code is determined in the processing unit by comparing it with a corresponding identification code read from a memory unit addressed by the code. In order to prevent line capacitance on the data bus simulating identification codes to produce an incorrect comparison, one line of the data bus is given the inverse data bit to that of an expected identification code to overcome any spurious bit due to line capacitance. If the identification code is present, the correct data bit in it prevails over the inverse data bit, resulting in a correct validity comparison. If there is no identification code, because there is no memory unit corresponding to the address code concerned, the inverse data bit remains, resulting in correct invalidity comparison.

Testing the presence of a peripheral device

Digital data apparatus comprising a processing unit which can have access to different numbers of memory units over a common data bus. The processing unit can address the memory units with select signals over individual leads of an address bus. Address codes containing select signals are valid when they select only a single memory unit. The validity of an address code is determined in the processing unit by comparing it with a corresponding identification code read over the data bus from a memory unit addressed by the code. Because an address code containing more than one select signal may select more than one memory unit, each address code has associated with it a number of flag bits which signify how many select signals the address code contains, and the corresponding identification code includes these flag bits. When an address code selects more than one memory unit there will be conflict on the data bus between the address code protions of the read identification codes. However, the flag bit portions of these read identification codes are not in conflict and can be compared with the flag bits associated with the address code being used to determine whether or not this address code is valid.

Digital data apparatus having a plurality of selectively addressable

As shown in FIG. 8, a phase shifter for phase shifting a single frequency clock signal CK as produced by an oscillator (813) comprises an inverter (805) and a delay network (804) for producing phase quadrature versions I.sub.ac, I.sub.ac and Q.sub.ac, Q.sub.ac of the signal. A current generator (803) produces control currents I.sub.c, I.sub.c and Q.sub.c, Q.sub.c, the magnitudes of which are determined by a control voltage V.sub.c whose magnitude represents a required phase shift. Two multipliers (801) and (802) multiply the signal pairs I.sub.ac, I.sub.ac and I.sub.c, I.sub.c ; and the signal pairs Q.sub.ac, Q.sub.ac and Q.sub.c, Q.sub.c, to produce resultant quadrature signals which are combined in an adder (806) to produce the phase shifted clock signal CLK (and CLK). The phase shift range is made to cover a number of cycles by an arrangement comprising two limit detectors (807) and (808), an OR-gate ( 809), a .div.2 circuit (810), and two reversing switches (811) and (812). This arrangement serves to reverse the sense of the control voltage V.sub.c at each limit of its operating range so that this range can be used successively a number of times to represent progressive phase shift. The current generator (803) can also be modified to provide control currents representing a phase shift of more than one cycle.

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Sutton, United Kingdom

John R Kinghorn