Delphi Technologies, Inc.

Delco Electronics Corporation

John R Fruth

Scott Birk Kesler

Mark Wendell Gose

Stephen P Barlow

Jerral A Long

Donald Ray Disney

Diane W Sidner

Michael Joseph Huemmer

Duane E Beyler

Dean M Dahlgnist

John Kevin Kaszyca

Thermal overload protection circuitryfor an automotive ignition system includes a gate drive circuit () responsive to a control signal (ESTB) to produce a drive signal (V) for driving a power switching device () separate from the protection circuitry (), and a thermal overload protection circuit () configured to supply a first current (I) to a thermal sensing component () associated with, and having an operating temperature defined by, the power switching device (), wherein the first current (I) has a magnitude defined by the operating temperature of the thermal sensing component (). The first current is multiplied by a current controlled current source () to produce a second current (I), and the second current is used to limit the drive signal (V) to thereby maintain the operating temperature of the power switching device () below an operating temperature limit.

Thermal overload protection circuit for an automotive ignition system

An interface for providing thermal overload protection includes a switching device, a temperature indicating device, a drive circuit and a thermal monitoring circuit. The thermal monitoring circuit is coupled across the temperature indicating device and provides a shutdown signal to the drive circuit when the temperature of the switching device is above a predetermined temperature level as indicated by a temperature signal provided by the temperature indicating device. The drive circuit responds to the shutdown signal by removing current sources and current sinks from a control terminal of the switching device at which point leakage currents cause the switching device to reduce a drive current to an inductive load.

Automotive ignition system with sparkless thermal overload protection

An integrated circuit () includes a thermal sensing device () and a power-switching device () such as an IGBT. The power device () is fabricated in a conventional manner on a semiconductor substrate, and the thermal sensing device () is fabricated on an electrical insulation layer () formed over the substrate. The thermal sensing device () may be provided in the form of a number of series-connected polysilicon diodes (D-D) positioned adjacent to the power device () such that the operating temperature of the thermal sensing device () is near that of the power device (). In response to an input current I, the thermal sensing device () produces an output voltage (V) that is substantially linear with surface die temperature, and which reacts rapidly to changes in surface die temperature. The thermal sensing device () is completely electrically isolated from the power device, thereby eliminating any electrical interaction therebetween.

Integrated circuit including semiconductor power device and electrically isolated thermal sensor

An apparatus and method for measuring leakage current between a first semiconductor region and a second semiconductor region to be formed therein includes a system for measuring surface minority carrier leakage within the first semiconductor region. A correlation is established between surface minority carrier lifetime in the first semiconductor region and leakage current between the first and second semiconductor regions, and in one embodiment a surface minority carrier lifetime threshold is designated based on this correlation. Leakage current between the first and second regions is acceptable if the measured surface minority carrier lifetime is greater than this threshold. In an alternate embodiment, a leakage current threshold is established, and the measured surface minority carrier leakage is converted via the correlation to a measured leakage current. Leakage current between the first and second regions is acceptable in this embodiment if the measured leakage current is less than the leakage current threshold.

Apparatus and method for determining leakage current between a first semiconductor region and a second semiconductor region to be formed therein

A semiconductor power device (100) that includes active cells in an interior region of an epitaxial layer (16) on a semiconductor substrate (12), and an edge termination structure that surrounds the cells and separates the cells from the die edge (48). A polysilicon layer (26) overlies and is electrically insulated from the epitaxial layer (16), a gate metal field plate (36) contacts the polysilicon layer (26), and a portion of the polysilicon layer (26) forms a gate for each cell. Each of the active cells also has a collector/anode terminal formed by the substrate (12), an emitter/cathode terminal formed by a well (18), emitter diffusion (20) and emitter metal (22), and a base formed by the epitaxial layer (16). The edge termination structure includes a first well (34) of a first conductivity type underlying the polysilicon layer (26) and completely surrounding the active cells, a second well (30) of an opposite conductivity completely surrounding the first well (34), and metallization (42) contacting the second well (30). The first well (34) is part of a low-voltage ring (28) while the second well (30) is part of a high-voltage ring. The wells (30, 34) are preferably spaced relative to each other and to the device edge (48) to provide ballast resistance through the epitaxial layer (16), such that a breakdown will not be able to generate enough localized current to damage or destroy the device (100) when a reverse power pulse is experienced.

IGBT power device with improved resistance to reverse power pulses

A semiconductor power device (100) that includes a number of bipolar or FET power devices (116), an over-voltage clamp (118), and an edge termination structure (110) that separates the power devices (116) and the over-voltage clamp (118). The power devices (116) are formed in an interior region (100a) of a semiconductor substrate (128), while the over-voltage clamp (118) is formed in a peripheral region (100b) of the substrate. The over-voltage clamp (118) and the gate/base terminals of the power devices (116) are formed in a polysilicon layer (126) overlying the substrate (128), such that the over-voltage clamp (118) is connected between the anode and gate/base terminals of each power device (116) to provide over-voltage protection. The edge termination structure (110) is formed in the substrate (128) so as to completely surround the interior region (100a) of the substrate (128), and therefore surrounds the power devices (116) to form a continuous barrier structure between the power devices (116) and the over-voltage clamp (118). The edge termination structure (110) includes a main junction (112) and at least one field-limiting ring (114), each of which is formed by a continuous well of the same electrical conductivity type. The edge termination structure (110) also includes a pair of field plates, a first (142) of which contacts the field-limiting ring (114) and a second (138) contacts the polysilicon layer (126) so as to make electrical contact with a gate terminal of the main junction (112).

Edge termination for zener-clamped power device

Disclosed are devices having emitters having resistive emitter diffusion sections are in a radial pattern. Such devices include vertical PNP power devices. The radial pattern of holes defines resistive emitter diffusion sections between adjacent holes. The resistive emitter diffusion sections result in a lower emitter ballast resistance due to the higher emitter sheet resistance of PNP devices. This allows all the periphery of the emitter to be active, not just two sides. The device has improved emitter ballast resistance while at the same time remaining efficient with low saturation resistance.

Vertical PNP power device with different ballastic resistant vertical

A protective circuit having enhanced and accurate thermal shutdown temperatures. The protective circuit establishes the thermal shutdown temperature within a predetermined range and provides an output signal when the thermal shutdown temperature is exceeded. The protective circuit, in one embodiment, comprises a current generator for supplying a predetermined collector current I.sub.c1, a current mirror arrangement for supplying a collector current I.sub.c2 which has a mirror response to that of the collector current I.sub.c1, a resistor arranged to have the mirror collector current I.sub.c2 flowing therethrough, and the combination of a resistor and a bipolar transistor serving as a thermal sensor. The current generator comprises at least a pair of bipolar transistors selected from one of the NPN and PNP types with each of said pair operating with different current densities. The base electrodes of the pair are interconnected by a resistor. The collector current I.sub.c1 flows through another resistor connected to the emitter electrode of one of said bipolar transistors. The current mirror arrangement has its mirror collector current determined by the value of the resistor at the emitter electrode of the bipolar transistor. The current mirror arrangement comprises bipolar transistors selected to be of the opposite NPN and PNP types as the current generator. The bipolar transistor serving as the thermal sensor is selected to be of the same type NPN and PNP as the current generator and has a known beta (.beta.) vs. V.sub.be relationship. The bipolar transistor is arranged in the output stage of the protective circuit and establishes a quantity V.sub.tsd which determines the thermal shutdown temperature. The V.sub.tsd quantity tracks the response of the beta (.beta.) parameter so as to cancel the effects that the variable V.sub.be parameter contributes to the thermal shutdown temperature.

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Kokomo, IN, United States of America

John R Fruth