Gennum Corporation

Macom Technology Solutions Holdings, Inc.

John R Francis

Atul Krishna Gupta

An amplifier with temperature compensation where the amplifier has transistors configured to amplify a received signal to create an amplified signal. The amplifier gain changes over temperature. A gain control circuit, connected to the amplifier, that adjusts the amplifier gain responsive to a gain control signal. A temperature compensation circuit includes numerous elements. A constant current source that generates a constant current which is used to create a constant voltage. A temperature dependent current source that generates a temperature dependent current which is used to create a temperature dependent voltage, such that the temperature dependent current source has an inverse temperature dependance as compared to the amplifier. An operational amplifier compares the constant voltage to the temperature dependent voltage and generates an offset signal which varies over temperature. A gated buffer is configured to receive the offset signal and responsive thereto, selectively modify the gain control signal.

Variable gain amplifier with temperature compensated gain

An improved phase detector for detecting the difference between an information signal and a clock signal is provided. The information signal is divided into a plurality of N divided signals, the data rate of each divided signal being the data rate of the information signal divided by N. A plurality of N variable width difference pulse signals are generated each being responsive to the phase difference between a divided signal and the clock signal. One or more fixed width reference pulse signals having a width proportional to one-half clock period are also generated. A phase error signal is then provided in response to the N difference pulse signals and the one or more reference pulse signals. Preferably, N is equal to 2.sup.M, where M is a positive integer greater than or equal to one.

Phase detector for high speed clock recovery from random binary signals

A control circuit for use with a phase locked loop in a digital video receiver. The digital receiver accepts a serial digital input signal which can comprise composite or component video signals. The phase locked loop comprises a phase detector, a loop filter, and a voltage controlled oscillator (VCO) and includes a divide-by-two modulus divider coupled to the output of the VCO. The VCO has an oscillation frequency control port and the divider has a frequency select port. The control circuit includes an automatic fine tuning and frequency sweeping stage which is coupled to the output of the loop filter and the oscillation frequency control port. The tuning and frequency stage provides temperature drift correction for the VCO. In addition, the tuning and frequency stage 'sweeps' the oscillation frequency of the VCO to aid in 'locking' the phase locked loop to the phase or frequency of the input signal. Once locked, timing signals and digital data can be extracted from the input signal. The control circuit also includes a video signal detector stage for detecting whether the input signal comprises a composite video signal or a component video signal. The video signal detector stage produces an output signal which controls the modulus of the divider in the phase locked loop.

Clock recovery circuit for serial digital video

An emitter-coupled oscillator circuit suitable for monolithic integration. The emitter-coupled oscillator circuit comprises (a) switching means for producing at an output port an output signal having a variable oscillation frequency, and the switching means has first and second inputs for receiving a differential control signal and the switching means includes first and second terminals for connecting to a capacitor; (b) output port means coupled to the output port of the switching means for outputting the output signal; (c) frequency control means coupled to the first and second terminals of the switching means for adjusting the oscillation frequency of the output signal; and (d) switching control means for producing a differential control signal at first and second outputs coupled to the first and second inputs respectively of the switching means and the switching means being responsive to the differential control signal for producing the output signal, and the switching control means having a control terminal coupled to the frequency control means.

Emitter-coupled oscillator with differential switching control

The switch has a cross-point. The cross-point has an input buffer, a level shift and an output buffer. The input and output buffers are BJT's, the level shift is two diode connected BJT's. The voltage drops across the buffers are designed to match the voltage drops across the diodes. The cross-point is enabled by a current source forcing current through the diodes. The matching of the voltage drops is effected by the Early voltage of the BJT's as they are operated at different V.sub.ce 's. An Early voltage determinator determines the effect of the Early voltage and adjusts the current flowing from the current source to force differing bias currents through the input buffer and the diodes to make the sum of the V.sub.be 's of each more independent of Early voltage. The output impedance of the current source and the impedance of the cross-point form a resistor-capacitor network. Where the f.sub..tau. of the current source is sufficiently low, the network has a pole-zero combination within the otherwise usable bandwidth of the switch. The current source has a first BJT at its output. A frequency compensating BJT is connected to the base of the first BJT, bringing the pole and zero closer together and shifting the pole-zero combination towards the upper limit of the otherwise usable bandwidth of the switch. A tally output is provided from the biasing network of the switch. The tally output provides an indication of the operating state,

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Burlington, Canada

John R Francis