Hewlett-packard Company

John R Feehrer

John A Morrison

Blaine Douglas Gaither

Eric M Rentschler

Michael S Allison

Stephen J Silva

Robert J Blakely

Leo J Embry

An apparatus and method for fault resilient booting of a multi-processor system. The apparatus attempts a cold reset of the system, during which each processor performs a built-in self test. The apparatus selects a boot strap processor to perform a warm reset, during which any failed processors are tristated using a flush command. If no boot strap processor is available, the apparatus performs the warm reset and tristates any failed processor including the processor predesignated to be the boot strap processor, and then repeats the attempt to establish the boot strap processor.

Apparatus and method for implementing fault resilient booting in a multi-processor system by using a flush command to control resetting of the processors and isolating failed processors

A device and method for recovery from address errors is described. When an address error is detected on a local channel, such as a local bus, the coherency states of one or more lines of cache memory associated with the local channel are read, and actions are taken in response. Reading of coherency states ranges from a complete and active interrogation of all cache lines, to a selective and passive interrogation, such as in responding to snoop requests. If the data state consistency is unknown, such as when the MESI state is Modified (M) or Exclusive (E), then the corresponding data in main memory is poisoned. Poisoning may be accomplished by writing a detectable but unrecoverable error pattern in the main memory. Alternatively, the same effect may be accomplished by signaling a hard error on the system bus. If the data state consistency of an interrogated cache line is Shared (S) or Invalid (I), the line may be ignored or the line marked invalid. If the state of the cached line is valid and consistent, such as the &ldquo;Modified uncached&rdquo; (Mu) state in a MuMESI protocol, then the line may be written to main memory or provided to a snoop requester.

System and method for recovery from address errors

An apparatus and method for permitting bus locking in a computer system having a mixed architecture. The mixed architecture includes a first bus coupled to processors that may run applications using bus locking or cache line locking. The apparatus interfaces the first bus with a second bus that does not support bus locking. The apparatus when presented with a locked transaction effectively implements bus locking on the second bus.

Mechanism for implementing bus locking with a mixed architecture

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Loveland, CO, United States of America

John R Feehrer