Oracle International Corporation

Oracle America, Inc.

Sun Microsystems, Inc.

Nvidia Corporation

John R Feehrer

Patrick Stabile

John Johnson

David M Kahn

Hugh R Kurth

Rahoul Puri

Julia D Harper

Matthew Cohen

Gregory Charles Onufer

Alan Adamson

Mark Douglas Hummel

Samuel Hammond Duncan

Glenn A Dearth

Denis J Foley

Daniel R Cassiday

Brian Kelleher

Vyas Venkataraman

Ram Gummadi

Pazhani Pillai

Tayfun Kocaoglu

Sriram Jayakumar

Sumti Jairath

Mark Donald Hill

John E Watkins

Ali Vahidsafa

David Allen Wood

Christopher J Jackson

Ramaswamy Sivaramakrishnan

Joseph Rollin Wright

Robert Dickson

Kenneth Chan

Aron J Silverton

Milton Shih

Peter Dunlap

Rick C Hetherington

Matthew G Noel

Boris Ostrovsky

Fred Han-Ching Tsai

Carl F Humphreys

Harry Stuimer

Jane W Yan

Hongping Li

Don M Morrier

Robert G Sheldon

Mark Kanda

Aruna Jayakumar

Ryan Benjamin Olivastri

Fabric Attached Memory (FAM) provides a pool of memory that can be accessed by one or more processors, such as a graphics processing unit(s) (GPU)(s), over a network fabric. In one instance, a technique is disclosed for using imperfect processors as memory controllers to allow memory, which is local to the imperfect processors, to be accessed by other processors as fabric attached memory. In another instance, memory address compaction is used within the fabric elements to fully utilize the available memory space.

Techniques for an efficient fabric attached memory

A method and apparatus for performing memory access operations during a memory relocation in a computing system are disclosed. In response to initiating a relocation operation from a source region of memory to a destination region of memory, copying one or more lines of the source region to the destination region, and activating a mirror operation mode in a communication circuit coupled to one or more devices included in the computing system. In response to receiving an access request from a device, reading previously stored data from the source region, and in response to determining the access request includes a write request, storing new data included in the write request to locations in both the source and destination regions.

Input/output direct memory access during live memory relocation

A method and system for processing data are disclosed. A processor, in response to executing a software program, may write an entry in a work queue. The entry may include an operation, and a location of data stored in an input buffer, and a location in an output buffer to write processed data. The processor may also generate a notification that at least one entry in the work queue is ready to be processed. The data transformation unit may assign the entry to a data transformation circuit, and retrieve the data from the input buffer using the location. The data transformation unit may also perform to the operation on the retrieved data to generate updated data, generate a completion message in response to completion of the operation, and store the updated data in an output buffer. An interface unit may relay transactions between the processor and the data transformation unit.

Hardware accelerated data processing operations for storage data

A system that allows access to a virtualized device is disclosed. The system may include a device, a processor, and a communication unit coupled to the device via a communication link. The device may include hardware resources configured to be shared by multiple threads executing on the processor. The communication unit may be configured to detect a request to access the device by the processor. In response to the detection of the request, the communication unit may send one or more instructions to the device via the communication link using a communication protocol.

Integration of a virtualized input/output device in a computer system

An apparatus and method for controlling a virtualized endpoint device are disclosed. A processor may be configured to execute instructions included in multiple execution threads. A first device may be configured to perform multiple command and data functions, and a communication unit may include a first port coupled to the first device via a first link and be configured to send instructions from the processor to the first device via the first link using a first communication protocol. The processor may be further configured to execute first and second sets of commands included in respective execution threads. The first set of commands may be associated with the plurality of command functions and the second set of commands may be associated with the plurality of data functions.

Separation of control and data plane functions in SoC virtualized I/O device

An apparatus and method for controlling a device with shared hardware resources to provide separate execution environments for control and data functions are disclosed. A processor may be configured to generate a first request to access control functions of the device in response to execution of a first thread, and generate a second request to access data functions of the device in response to execution of a second thread. A communication unit may send first indicative of the first request and second data indicative of the second request to the device via first and second ports, respectively.

Embodiments of input/output hub unit are disclosed for aggregating interrupts received from multiple endpoint devices. The input/output hub may include an interface unit and one or more communication units. Each communication unit may be configured to receive messages from a corresponding endpoint device. The interface unit may be configured to update a first pointer within a first data structure responsive to a request from a given one of the communication units. The interface unit may be further configured to stored data in a second data structure responsive to updating the first pointer, reading a second pointer and the first pointer, and sending an interrupt responsive to a determination that the first and second pointers are equal.

Aggregation of interrupts using event queues

An apparatus and method for resetting a virtualized device are disclosed. The virtualized device may be coupled to a first port on a communication unit via a first link. The first port may send one or more instructions to the virtualized device via the first link using a first communication protocol. A processor may be configured to detect a reset condition for the virtualized device. In response to the detection of the reset condition for the virtualized device, the first port may disregard one or more transaction requests made by the virtualized device. The first port may further send an error message to the processor in response to receiving a Programmed Input/Output (PIO) request from the processor after the detection of the reset condition.

Implementation of reset functions in an SoC virtualized device

A switched fabric hierarchy (e.g., a PCIe hierarchy) may utilize hardware, firmware, and/or software for filtering duplicative or otherwise undesirable correctable error messages from reaching a root complex. An operating system of the root complex may detect a persistent stream or storm of correctable errors from a particular endpoint and activate filtering of correctable errors from that endpoint. A filtering device may receive filtering commands and parameters from the operating system, implement the filtering, and monitor further correctable errors from the offending device. While an offending device is being filtered, correctable error messages from the offending device may be masked from the operating system, while correctable error messages from other devices in the switched fabric hierarchy may be transmitted. At such time as the filtering device may detect that conditions for ending filtering of a device are met, the filtering device may cease filtering of the offending device and return monitoring responsibilities to the operating system.

Correctable error filtering for input/output subsystem

Implementations of the present disclosure involve a system and/or method for handling errors in a multi-node commercial computing system running a number of guest applications simultaneously. In particular, the system and/or method provides the ability to program on a per-error basis the destination within the system for an interrupt based on an I/O error, the ability to provision for multiple/redundant error reporting paths for a class of more severe errors and/or distributed set of error status and log registers to aid software in narrowing down the source of an error that triggered the interrupt. In addition, the system provides for dynamically altering the destination of the error handling in response to one or more operating conditions of the system. Such flexibility in the system provides for a more robust error handling without impacting the performance of the multi-node computing system.

Selecting I/O interrupt target for multi-core server systems

An input/output hub may include an interface unit and one or more communication units. Each communication unit may be configured to receive interrupts or messages from a corresponding endpoint device. A given communication unit may be further configured to synthesize a virtual address from the received message, translate the synthesized virtual address to a real address, and then translate the real address to a physical address. The interface unit may be configured to send an interrupt dependent upon the physical address.

Virtualizing input/output interrupts

Growing community of inventors

Westford, MI, United States of America

John R Feehrer