Intel Corporation

John R Fastabend

Brian J Skerry

Iosif Gasparakis

Daniel Daly

Ronen Chayat

Danny Yigang Zhou

Matthew Vick

Marco Varlese

Jing Mark Chen

Kapil Sood

Jeffrey B Shaw

Patrick L Connor

Sanjeev Jain

Mesut A Ergin

Nrupal R Jani

Neerav Parikh

Shinae Woo

Calin Gherghe

David J Harriman

Ren Wang

Christian Maciocco

Ben-Zion Friedman

Ilango S Ganga

Elizabeth M Kappler

Dinesh Kumar

Eric W Multanen

Jr Brian J Skerry

Technologies for controlling operation of a compute node coupled to a computer network via a computing device that includes communications for communicating with the computer network and persistent instructions such as firmware for providing control functions to the computing device, wherein the control functions being defined at least in part by protocol data. An update control module of the computing device may receive update data from a remote node in the computer network via the communications, wherein the update data comprising new protocol data for the persistent instructions. A protocol parser module may parse the update data and generate metadata relating to the update data. A classifier module may receive rules for the control functions, wherein the rules are based at least in part on the update data and metadata. A compiler may compile the parsed update data to the persistent instructions for providing new control functions to the computing device based at least in part on the received rules.

Programmable protocol parser for NIC classification and queue assignments

Devices and techniques for accelerated packet processing are described herein. The device can match an action to a portion of a network data packet and accelerate the packet-processing pipeline for the network data packet through the machine by processing the action.

Accelerated network packet processing

Devices and methods for debugging software or detecting malicious software on a compute node are described herein. A device can include an interface to a central processing unit (CPU) of a compute node. The device can include processing circuitry. During execution of a software application of the CPU, the processing circuitry can process CPU operational metrics received over the interface, wherein values of the CPU operational metrics vary with execution of the software application. Based on the values, the processing circuitry can determine an operational status of the software application and provide an indicator of an error condition of the software application responsive to detection of an error based on any criteria. Other embodiments are also described.

Software condition evaluation apparatus and methods

Technologies for secure inter-virtual network function communication include a computing device to determine a cryptographic key for secure communication over at least one of an inter-virtual network function (VNF) network, an inter-virtual network function component (VNFC) network, or a VNF-VNFC network based on a security policy of the computing device; and. The computing device securely communicates over at least one of the inter-VNF, inter-VNFC, or VNF-VNFC network based on the determined cryptographic key.

Technologies for secure inter-virtual network function communication

Technologies for distributed detection of security anomalies include a computing device to establish a trusted relationship with a security server. The computing device reads one or more packets of at least one of an inter-virtual network function network or an inter-virtual network function component network in response to establishing the trusted relationship and performs a security threat assessment of the one or more packets. The computing device transmits the security threat assessment to the security server.

Technologies for distributed detection of security anomalies

Devices and techniques for hardware accelerated packet processing are described herein. A device can communicate with one or more hardware switches. The device can detect characteristics of a plurality of packet streams. The device may distribute the plurality of packet streams between the one or more hardware switches and software data plane components based on the detected characteristics of the plurality of packet streams, such that at least one packet stream is designated to be processed by the one or more hardware switches. Other embodiments are also described.

Apparatus and method for hardware-accelerated packet processing

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Hillsboro, OR, United States of America

John R Fastabend