Nxp B.v.

Koninklijke Philips Corporation N.v.

U.S. Philips Corporation

Koninklijke Phillips Electronics N.v.

John R Cutter

Brendan P Kelly

Cornelis Eustatius Timmering

Erwin A Hijzen

A field transistor is divided into a number of cells () and includes a separate first gate line () connected to first transistor cells () and a separate second gate line () connected to second transistor cells (). A drive circuit is used to drive all the cells () in a normal, saturated operations state but to drive only the second cells () in a linear operations state to reduce the number of cells used in the linear operations state.

Field effect transistor circuit and method of operation of field effect transistor circuit for reducing thermal runaway

A driver for an inductive load such as a solenoid coilincludes three FETsTwo of the FETs are reversely connected between battery and output terminalsand one of the FETs is connected between output and ground terminalsA driver circuithaving high and low side control circuitryis formed in a common substrate with two of the FETsIn use, a coilis connected to the output terminaland driven in an energize mode in which current in the coilis built up as indicated by arrowa freewheel mode in which current circulates freely as indicated by arrowand then may be switched off. The reversely connected FETs allow both short circuits to be prevented in the energize mode and allow the coil to be rapidly switched off. In spite of the control circuitry being formed in a common substrate with some of the FETs, the arrangement allows the FETs to be properly driven.

Driver for inductive load

Thermal cycling can lead to damaging stress at the upper surface of a semiconductor device chip ( ) encapsulated in synthetic resin material ( ), particularly in the case of power devices that include an IC. The invention provides a thick ductile layer pattern ( ) of, for example, aluminium over most of the top surface of the insulating over-layer ( ) of the chip ( ). Electrically-isolated parts ( etc.) of this ductile covering are individually connected to respective underlying conductive areas so as to reduce charging effects across the insulating over-layer ( ). A sufficient spacing Z is present between these isolated parts ( etc.) to avoid short circuits as a result of deformation by shearing and smearing during thermal cycling of the device. The ductile metal layer pattern ( ) reduces stress between the insulating material ( ) and the plastic material ( ), but it can be both easily and cheaply applied in device manufacture before dividing the wafer into individual chips.

Semiconductor devices and their manufacture

In the manufacture of a trench-gate semiconductor device, for example a MOSFET or an IGBT, a starting semiconductor body ( ) has two top layers ( ) provided for forming the source and body regions. Gate material ( &prime;) is provided in a trench ( ) with a trench etchant mask ( , FIG. ) still present so that the gate material ( &prime;) forms a protruding step ( ) from the adjacent surface ( ) of the semiconductor body, and a side wall spacer ( ) is then formed in the step ( ) to replace the mask ( ). The source region ( ) is formed self-aligned with the protruding trench-gate structure with a lateral extent determined by the spacer ( , FIG. ), and the gate ( ) is then provided with an insulating overlayer ( , FIG. ). Forming the sidewall spacer ( ) when the protruding trench-gate structure has a well-defined edge provided by the gate material ( &prime;) allows better definition of the source region ( ) compared with a prior-art process in which the gate insulating overlayer is provided in the trench before causing the trench-gate structure to have the protruding step for the sidewall spacer.

Manufacture of trench-gate semiconductor devices

In a MOSFET or other high voltage device, an annular channel stopper (4) extends around the outer periphery (14) of a body portion (11) with which a device region (15) forms a p-n junction (5) operable under high reverse bias in at least one mode of operation of the device. A field plate structure (34, 34a, 34b, 34c) on an insulating layer (24) over the body portion (11) extends towards the outer periphery (14) to spread a depletion layer from the reverse-biased p-n junction (5) towards the outer periphery (14). The channel stopper (4) comprises concentrically doped stopper regions (41 to 44) with different doping concentrations and/or region widths and/or spacings, giving to the body portion (11) a non-uniform doping profile the doping of which, under the field plate structure (34, 34a, 34b, 34c), increases with distance (D) towards the outer periphery (14) to slow progressively the spread of the depletion layer under the field plate structure (34, 34a, 34b, 34c). This field plate structure (34, 34a, 34b, 34c) connected to the device region (15) and/or to a field region (35) can extend laterally over the whole of the body portion (11) between the device region (15) and a doped channel stopper region (41) in the vicinity of the outer periphery (14), and without the complication of any field plate connected to the channel stopper (4).

Growing community of inventors

Macclesfield, United Kingdom

John R Cutter