Rixon Inc.

Case Communications Inc.

John R Cressey

Dennis C Meneely

Stephen A Miller

Characteristics of a pulse sequence, such as frequency, are controlled in a simple circuit without requirement for specific storage components. The cumulative effect of a sequence of control signals is maintained by providing a phase shift between a pair of waveforms. The phase shift between the waveforms is used to provide a number of control pulses to the circuit for varying the desired characteristic. In a particular embodiment, control signals are externally provided for varying the phase shift between two waveforms. In response to the phase variation, a number of control signals are provided for adding or deleting pulses to a pulse stream. The use of feedback control loops results in repeated addition and/or deletion of pulses to or from the pulse stream, thereby varying the output frequency in accordance with a one time input of the external control signals. In accordance with the principles of the invention, serial or parallel control signals may be provided, and ripple counters (or a combination of ripple and presettable counters) may be used for the frequency control function.

Variable digital frequency generator with value storage

Circuitry for decoding differential phase shift keyed signals utilizes a counter, having a capacity selected such that in an integration interval having a duration equivalent to one-half the period of a reconstructed carrier, a full count and resultant rollover identifies a decision threshold for information descriptive of the received signal. At the conclusion of the integration interval, the contents of the counter represent half a full count thereof for no phase error in the reconstructed carrier. Phase error in the carrier is determined during a subsequent interval by counting up of the same counter to achieve a reset condition thereof. The counter is counted up until occurrence of a rollover signal, which signal is used to prevent passage of any further pulses to the counter and to maintain the counter in an all zero state. At the input, a hard limited version of the modulated signal is provided to an EXCLUSIVE OR gate together with the reconstructed carrier in order to provide decoding intervals for counting of clock pulses by the counter during the preset integration intervals.

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College Pk., MD, United States of America

John R Cressey