Koninklijke Philips Corporation N.v.

Tpo Hong Kong Holding Limited

Chimei Innolux Corporation

John R A Ayres

Martin John Edwards

Nigel David Young

Alan G Knapp

Keitaro Yamashita

Stephen J Battersby

Stanley D Brotherton

Carole A Fisher

Michael J Trainor

Frnak W Rohlfing

An active matrix array device has driver circuitry for providing address signals to the matrix elements, including digital to analogue converter circuitry. This has a voltage selector for selecting a pair of voltages based on a first set of bits of the digital matrix element signal, and a converter arrangement for providing an analogue voltage level derived from the pair of voltages and from a second set of bits of the digital matrix element signal. The converter arrangement comprises first and second digital to analogue converter circuits () in parallel and which are adapted to provide an analogue voltage level to an output of the converter arrangement alternately. The invention provides a more efficient use of substrate area for given circuit response requirements.

Active matrix array device

An active matrix display has a column driver for providing signals to the pixels for driving the display elements, the column driver comprising digital to analogue converter circuitry providing a first number of display element drive levels. Within each pixel, the first number of display element drive levels is converted into a second, greater number, of pixel grey levels. This combines multi-level digital to analogue conversion with in-pixel level generation and enables the complexity of the DACs to be reduced so that they can be integrated onto the display substrate, for example using low temperature polysilicon processing.

Active matrix display

An amplification circuit comprises a capacitor arrangement () and a switching arrangement. The capacitor arrangement has a first capacitor (C) which has a voltage-dependent capacitance and a second capacitor (C) (which may also be voltage-dependent). The circuit is operable in two modes, a first mode in which the input voltage is provided to one terminal of at least the first capacitor, and a second mode in which the switching arrangement causes charge to be redistributed between the first and second capacitors such that the voltage across the first capacitor changes to reduce the capacitance of the first capacitor, the output voltage being dependent on the resulting voltage across the first capacitor. The invention uses a voltage controlled capacitance in combination with charge sharing between capacitors, which has the result of providing a voltage amplification characteristic. This arrangement can thus be used for the amplification of an analogue voltage, or the boosting of a fixed level (i.e. digital voltage). Thus, the circuit of the invention can be used for level shifting or amplification, for example for use in the pixels of an active matrix array device.

Circuit for signal amplification and use of the same in active matrix devices

An active matrix array device has a plurality of matrix array elements (), each of which have a first capacitive device () coupled to a charging conductor () via a first switch () being responsive to an addressing conductor (). In addition, the matrix array elements () comprise a second capacitive device () coupled to the first capacitive device () via a second switch () being responsive to en enable signal provided via an enable conductor (). The second capacitive device () is coupled to the control terminal of a third switch (), which is coupled between the first capacitive device () and a potential source like the charging conductor (). The second capacitive device () is used to sample the voltage across the first capacitive device (), which enables the third switch () if of an appropriate value, thus providing a conductive path between the first capacitive device () and the potential source. This arrangement allows for a low-power data refresh mode of the matrix array elements () with polarity inversion in subsequent refresh cycles.

Active matrix array device, electronic device and operating method for an active matrix array device

A charge pump circuit has a voltage increasing stage and a voltage decreasing stage in parallel, and sharing a common input. This shows charge to flow between the stages, so that charge used in the pumping of one stage is recycled to the other stage.

Charge pump circuit

A display device with capacitive display pixels, in which a drive scheme is used for capacitive coupling of voltages to enable reduced column voltage swings to be obtained. Each pixel has two storage capacitors. The use of two storage capacitors provides some freedom in the choice of the magnitude of the voltage swing provide on one terminal of one of the storage capacitors. The first capacitor (C) of all pixels of the display may be grounded, and only the second capacitor (C) is subjected to changes in voltage to be capacitively coupled to the display cell. This provides a flexible capacitor line drive type scheme.

Active matrix display device

An active matrix device includes a plurality of display elementsincluding a data storage nodefor storing data in the form of charge on a capacitorand/or capacitative element. Refresh circuitryis provided to refresh the data storage node, for example including temporary storage circuitand drive circuit

Active matrix array devices

A pixellated device (), such as a display, has pixel row and column address lines () for addressing each pixel, thereby providing signal data to each pixel () or reading signal data from each pixel. An array of memory cells () is provided on the substrate interspersed with the pixel drive circuitry (), wherein memory address circuitry () is provided enabling data to be written to each memory cell and enabling data to be read from each cell (), independently of the signal data. Each memory cell () is thus addressable independently of the pixel data. Thus, the memory cells do not form part of the pixel circuitry, which allows the memory to be used in a flexible manner. For example, the memory may be used for purposes not directly associated with the driving or addressing of the pixels of the device.

Pixel array with indirectly associated memory

An active matrix display device includes a plurality of pixels () arranged as rows and columns and column electrodes () extending along corresponding columns of pixels (). The pixels include a capacitance () for storing image data and a read circuit for reading the charge stored on the capacitance () and driving the column electrode with the read charge.

Active matrix display devices

An active matrix substrate includes a row and column array of active elements. Each element is associated with a TFT having a gate electrode connected to a corresponding row conductor and source and drain (electrodes connected to corresponding column conductors. Circuitry for protecting against electrostatic discharge (ESD) is connected to at least one of the row conductors for protecting the TFTs against ESD.

Active matrix substrate

A method of fabricating an electronic device comprising a thin-film transistor, which addresses a problem of increased off-state current and reduced carrier mobility in self-aligned thin-film transistors. According to the method, a gate layer ( ) is etched back underneath a mask layer ( ). Following an implantation step using the mask layer as an implantation mask, the etch-back exposes implant damage which is then annealed by an energy beam ( ).

Electronic device manufacture

A charge pump circuit ( ) comprises a series of voltage boosting stages ( ), each stage ( ) comprising a switching means ( ) and a capacitive element ( ) connected in series between the input to the stage and a respective voltage control terminal ( ). The voltage control terminals ( ) comprise at least two groups of terminals receiving respective timed control voltages, and adjacent stages ( ) are associated with different terminal groups. The switching means ( ) of one or more stages ( ) comprises a lateral PIN junction diode. The use of diodes enables the charge pump circuit itself to operate from a lower supply voltage than is possible with the use of TFTs. The use of lateral PIN diodes enables the charge pump circuit to be formed using the same processing as may be required for TFT's of the circuit to which the boosted voltage is supplied. This enables the charge pump circuit to be formed on a common substrate with higher voltage TFT circuitry for, for example, an AMLCD.

Growing community of inventors

Reigate, United Kingdom

John R A Ayres