Emc Corporation

John Phinney

Stephen Edward Strickland

Steven D Sardella

Lawrence J Feroli

Avinash Kallat

Amnon Izhar

Jonathan C Giffen

James Creighton Tryhubczak

Kenneth M Sullivan

Kranti Uppala

Adrianus Djohan

An arrangement having a processor electrically to, and mounted on, a portion of a surface of a motherboard. A plurality of memory cards is plugged into memory board slot type connectors on a surface of the memory card printed circuit board with the surface of the memory card printed circuit board being perpendicular to the surface of the motherboard. A right angle backplane connector has a first end disposed perpendicular to, and electrically connected to the surface of a motherboard and a second end disposed on the surface of, and electrically connected to, the memory card printed circuit board. The plurality of memory cards is parallel to the surface of the motherboard. An ejector mechanism is provided for removing the memory printed circuit board from an electrical connector receptacle mounted to the motherboard by camming action.

Memory interconnect arrangement having high data transfer speed signal integrity

Described are electronics systems and methods for distributing a limited number of lanes of a PCI Express-based processor (CPU) module among a plurality of PCI Express-based I/O modules with which the CPU module is in communication. The CPU module receives a code from each I/O module over a sideband interface between that I/O module and the CPU module. The coded signal represents a link-width capability of the I/O module. The CPU module is configured to allocate a link width to each I/O module based on the fixed number of lanes and the link-width capability as represented by the coded signal received from that I/O module. The link between CPU module and each I/O module is trained in accordance with the link width allocated to that I/O module.

Interface for establishing operability between a processor module and input/output (I/O) modules

An interrupt controller enables multiple CPUs to control access to an increased number of interrupts. Each of a plurality of CPUs is able to block interrupts written to the interrupt controller at multiple levels. First, each CPU is able to block interrupts at the interrupt level. In other words, a CPU is able to block one or more individual interrupt requests from I/O devices from being sent to that CPU. Second, each CPU is able to block interrupts from one or more entire MSI interrupt registers from being sent to that CPU. The interrupt controller is fully programmable by the CPUs in software and thus is very flexible, as the priority of interrupts can be controlled by the CPUs according to the requirements of the CPUs based on the various operational demands of the CPUs. Any of 512 possible interrupt requests are capable of being routed to any particular one CPU, any combination of the CPUs or to all of the CPUs.

System for controlling interrupts between input/output devices and central processing units

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Westford, MA, United States of America

John Phinney