Juniper Networks, Inc.

Azul Systems, Inc.

John Phillips

Nazar A Zaidi

Elango Ganesan

Michael Freed

Ramesh Panwar

Mark Bryers

Yen C Lee

Sankar Ramanoorthi

Yuhong Zhou

Gregory G Spurrier

David T Hass

Robert G Hathaway

Abbas Rashid

Frederick R Gruner

Ricardo Ramirez

Mark Vilas

Chau Anh Ngoc Nguyen

Kevin B Normoyle

Sreenivas Aerra Reddy

Chau Ahn Ngoc Nguyen

A network content service apparatus includes a set of compute elements adapted to perform a set of network services; and a switching fabric coupling compute elements in said set of compute elements. The set of network services includes firewall protection, Network Address Translation, Internet Protocol forwarding, bandwidth management, Secure Sockets Layer operations, Web caching, Web switching, and virtual private networking. Code operable on the compute elements enables the network services, and the compute elements are provided on blades which further include at least one input/output port.

Content service aggregation system

An architecture for controlling a multiprocessing system to provide at least one network service to subscriber data packets transmitted in the system using a plurality of compute elements, comprising a management compute element including service set-up information for at least one service and at least one processing compute element applying said at least one network service to said data packets and communicating service set-up information with the management compute element in order to perform service specific operations on data packets. In a further embodiment, a method of controlling a processing system including a plurality of processors is disclosed. The method comprises the steps of operating at least one of said processors as a control authority providing service provisioning information for a subscriber; and operating a set of processors as a service specific compute element responsive to the control authority, receiving provisioning information from the subscriber and performing service specific instructions on data packets to provide IP content services.

Content service aggregation device for a data center

A system chip has many local blocks including processor cores, caches, and memory controllers. Each local block has a local sample-select mux that is controlled by a local selection control register. The mux selects from among hundreds of internal sample nodes in the local block, and can also pass through samples output by an upstream local block. The selected samples from local blocks are sent to a central on-chip logic analyzer that compares the samples to a maskable trigger value. When the trigger value is matched, a trigger state machine advances, and samples are stored into a central capture buffer. A user debugging the chip can later read out the central capture buffer at a slower speed. Thousands of internal nodes from local blocks can be selected for sampling, triggering, and debugging. Local blocks include valid bits in 64-bit-wide samples. Only valid samples are written to the capture buffer.

Wide-scan on-chip logic analyzer with global trigger and interleaved SRAM capture buffers

Growing community of inventors

Santa Clara, CA, United States of America

John Phillips