National Semiconductor Corporation

John Philip Parry

William James McIntyre

Nathanael Griesert

Jeff Kotowski

Arun Rao

Alexander Burinskiy

James Charles Schmoock

A circuit and method for charging a super capacitor to an optimal voltage that provides a desired flash diode current value while minimizing power dissipation in circuit elements other than the flash diode. One embodiment uses periodic sampling of the current through the flash diode and termination of the charging upon the super capacitor having been charged to a voltage value that produces the desired flash diode current. Another embodiment includes a current regulator in the flash diode firing circuit that keeps the current at a substantially constant level during the time that the flash diode is being fired.

Method and circuit for charging of super capacitor as energy source for flash diodes

A switch array circuit that enables voltage regulation by bucking a relatively larger input voltage as it declines over time with different fractional gains that are based on different gain phase arrangements for a plurality of capacitors. A common rest phase is provided during the switching between the different gain phases. The rest phase inherently enables power to be conserved during gain transitions. Increasingly larger fractional gain phases (less buck) is provided as the input voltage declines over time, e.g., from &#x2153; to &#x2156; to &#xbd; to &#x2154; to unity, and the like. Also, the common rest phase for the plurality of capacitors is arranged to minimize fluctuation of the output voltage during switching between phases to generate a selected gain from the gain phase. Additionally, the common rest phase conserves/stores energy during switching transitions between multiple gain phases. The stored energy in the common rest phase can be subsequently reused in the gain phases.

Fractional gain circuit with switched capacitors and smoothed gain transitions for buck voltage regulation

A multi-stage transistor circuit is provided in which the multiple transistor stages are coupled in parallel and switched individually in sequence by a series arrangement of buffers. Each buffer drives the gate of a corresponding stage of the multi-stage transistor circuit with a gating signal that is delayed by each buffer. Optionally, the voltage of the gating signal can be varied. Each transistor stage may comprise one or more transistors in parallel. A switched capacitor DC/DC converter incorporating the multi-stage transistor circuit is provided in which parasitic ringing at the output is substantially reduced or eliminated. Additionally, the multi-stage transistor circuit is well suited for implementing an adaptive non-overlapping gating signal generator for complementarily driving a series arrangement of multi-stage transistors. An adaptive gating signal generator incorporating the multi-stage transistor circuit provides the minimum dead time between the gating signals that will ensure under all conditions that the multi-stage transistors will not be on at the same time.

Suppression of parasitic ringing at the output of a switched capacitor DC/DC converter

An integrated circuit including one or more power devices, and circuitry which reliably (and independently) shuts down each power device that is detected to be in an undesired operating condition (e.g., one or both of an overcurrent condition and an overvoltage condition) that causes a thermal fault, but which does not shut down any power device that is not in such undesired operating condition. In typical implementations in which the integrated circuit has multiple power devices and an overvoltage detection circuit for each power device, the integrated circuit includes a thermal fault detection circuit and logic circuitry which receives the output of the thermal fault detection circuit and each overvoltage detection circuit. The logic circuitry generates signals which shut down appropriate ones of the power devices in response to the thermal fault detection and overvoltage detection signals it receives. The integrated circuit also includes fail safe thermal shutdown circuitry which shuts down all power devices upon detecting a more severe thermal fault even when no overcurrent or overvoltage condition is detected. In some embodiments, when a thermal fault is detected, each power device that is in an overcurrent and/or overvoltage condition (but none of the power devices that is in neither an overcurrent nor an overvoltage condition) is shut down. All the power devices are shut down upon detection of a more severe thermal fault even when no overcurrent or overvoltage condition is detected.

Apparatus for selective shutdown of devices of an integrated circuit in response to thermal fault detection

A structure and method are provided for converting unregulated DC voltages to regulated DC voltages using pulse frequency modulation (PFM) and a switched capacitor array capable of multiple gains, where gain selection is based on the output voltage. The selected gain is maintained at or above a minimum gain determined from the input voltage. A regulated voltage, which is equal to or greater than a desired output voltage, is thus available to the load over a wider range of inputs and with greater conversion efficiency.

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Grass Valley, CA, United States of America

John Philip Parry