Arm Limited

John Philip Biggs

James Edward Myers

Jedrzej Kufel

David Walter Flynn

Emre Özer

Remy Pottier

David William Howard

Emre Ozer

Shidhartha Das

George McNeil Lattimore

Bal S Sandhu

Robert Campbell Aitken

Mbou Eyole

Vikas Chandra

Parameshwarappa Anand Kumar Savanth

Carsten Tradowsky

Dhrumil Gandhi

Gavin Brown

Charles Edward Michael Reynolds

Adrian Reece Wheeldon

Apparatus comprises at least one visual indicator element; at least one detector to detect access to the apparatus consistent with a cleaning operation being applied to a surface of the apparatus; and processing circuitry to control a visual indication state of the at least one visual indicator element in response to a detection by the detector of access to the surface of the apparatus.

Circuitry and method

Battery cell monitoring systems comprising a flexible substrate and components integrated onto the flexible substrate, and methods of operating the same are disclosed. The components comprise a computing device and at least one sensor, where the at least one sensor is configured to generate sensor signals indicative of a physical state of the battery cell. The computing device is configured to hold characteristic data values which have been generated based on prior sensor signals. The computing device is configured to receive the sensor signals from the at least one sensor and to generate battery cell status data in dependence on the sensor signals and the characteristic data values.

Battery cell monitoring systems, battery packs, and methods of operation of the same

Methods of performing post-manufacturing adaptation of a data processing apparatus manufactured in accordance with a processor design and corresponding data processing apparatus configurations are provided. Post-manufacturing testing of the data processing apparatus determines any dysfunctional instructions by comparison between component usage profiles for each instruction and a component fault-detection procedure applied to the data processing apparatus. The data processing apparatus can be determined nevertheless to be operationally viable when any dysfunctional instructions can be substituted for by emulation using other functional instructions. The data processing apparatus can be provided with dysfunctional instruction handling circuitry configured to identify occurrence of a program instruction instance of a dysfunctional instruction and to invoke an interrupt handling routine associated with the dysfunctional instruction to emulate the instance of a dysfunctional instruction.

Post-manufacturing adaptation of a data processing apparatus

Apparatuses and methods of operating such apparatuses are disclosed. An apparatus comprises feature dataset input circuitry to receive a feature dataset comprising multiple feature data values indicative of a set of features, wherein each feature data value is represented by a set of bits. Class retrieval circuitry is responsive to reception of the feature dataset from the feature dataset input circuitry to retrieve from class indications storage a class indication for each feature data value received in the feature dataset, wherein class indications are predetermined and stored in the class indications storage for each permutation of the set of bits for each feature. Classification output circuitry is responsive to reception of class indications from the class retrieval circuitry to determine a classification in dependence on the class indications. A predicated class may thus be accurately generated from a simple apparatus.

Feature dataset classification

A battery cell monitoring system comprises a flexible substrate able to conform to a surface of a battery cell to be monitored, and a plurality of first-level prediction units integrated onto the flexible substrate, where each first-level prediction unit is positioned at a different location on the flexible substrate to each other first-level prediction unit. Each first-level prediction unit comprises at least one sensor to generate sensor signals indicative of a physical state of the battery cell, and first-level prediction circuitry to generate a predicted battery cell status value in dependence on the sensor signals received from the at least one sensor of that first-level prediction unit. Second-level prediction circuitry is arranged to determine a prediction result in dependence on the predicted battery cell status values generated by the first-level prediction circuitry of each first-level prediction unit, and a communications device is used to output the prediction result at least when the prediction result indicates an occurrence of a critical event.

Technique for monitoring a battery cell

Wearable items and methods of monitoring wearable items are disclosed. The wearable item comprises a flexible base material forming at least a portion of the wearable item, plural conductive traces traversing the flexible base material, and conductivity sensing circuitry coupled to the plural conductive traces. The conductivity sensing circuitry is configured to distinguish conductivity from non-conductivity of the plural conductive traces, and configured to generate a conductivity indication for at least one of the plural conductive traces. The plural conductive traces follow indirect paths across the flexible base material, allowing the flexible material to flex and stretch normally without breaking the conductive traces.

Integrity monitoring for flexible material

Aspects of the present disclosure relate to an apparatus comprising: a substrate; communication circuitry deposited on said substrate; and ballot circuitry deposited on said substrate. The ballot circuitry comprises: a plurality of voting circuitry elements, each voting circuitry element being responsive to a voting operation to change a conductive state of that voting circuitry element; and logic circuitry communicatively coupled with each of the plurality of voting circuitry elements and with the communication circuitry. The logic circuitry is configured to: detect the conductive state of each of the plurality of voting circuitry elements; and transmit, via the communication circuitry and based on the conductive state of each of the plurality of voting circuitry elements, a voting result.

Methods and apparatus for electronic voting

According to one embodiment of the present disclosure, a device comprises a latching circuitry, where the latching circuitry comprises at least one correlated electron random access memory (CeRAM) element. The latching circuitry further comprises a control circuit coupled to the at least one CeRAM element. The control circuit is configured to receive at least one control signal. Based on the at least one control signal, perform at least one of storing data into the latching circuitry and outputting data from the latching circuitry.

CES-based latching circuits

Apparatuses, methods of operating apparatuses, and corresponding computer programs are disclosed. In the apparatuses input circuitry receives input data comprising at least one data element and shift circuitry generates, for each data element of the input data, a bit-map giving a one-hot encoding representation of the data element, wherein a position of a set bit in the bit-map is dependent on the data element. Summation circuitry generates a position summation value for each position in the bit-map, wherein each position summation value is a sum across all bit-maps generated by the shift circuitry from the input data. Maximum identification circuitry determines at least one largest position summation value generated by the summation circuitry and output circuitry to generate an indication of at least one data element corresponding to the at least one largest position summation value. The statistical mode of the data elements in the input data is thereby efficiently determined.

Statistical mode determination

Integrated circuits () are manufactured by printing an array of circuit elements CE each containing an integrated circuit and associated testing circuitry (). A plurality of integrated circuits within the array are tested in parallel to generate a corresponding plurality of individual test result signals. These individual test result signals are combined to form a combined test result signal indicating whether any of the plurality of integrated circuits tested in parallel operated incorrectly during their testing. If the combined test result signal indicates any faulty integrated circuits, then the entire plurality of integrated circuits (e.g. an entire row or column) may be discarded. The array of tested integrated circuits are then separated into discrete integrated circuits and are also separated from their testing circuit. Contacts () providing power signals, clock signals, and the reading of the combined test result signals are located at the periphery of a substrate sheet onto which the array of circuit elements are printed.

Testing an array of integrated circuits formed on a substrate sheet

Disclosed herein is an apparatus that includes a first pair of signal lines and a second pair of signal lines. Each pair of signal lines comprises a first line and a second line that collectively signal any one of: a logical zero, a logical one, and nothing. A first cell occupies a first layer of the apparatus to receive the first line of the first pair of signal lines and the first line of the second pair of signal lines; and a second cell occupies a second layer of the apparatus to receive the second line of the first pair of signal lines and the second line of the second pair of signal lines. The first cell is a dual of the second cell and at least partially overlaps the second cell.

Integrated circuit design

A circuit comprises an array of programmable memory elements fabricated on a substrate, each memory element having one or more processable regions which, when processed by an external process in which a material is applied to at least partially cover one or more of the regions, are configured to program that memory element to one of multiple states; a first set of control lines connected to the array of memory elements, by which the contents of each individual memory element are capable of being accessed by control signals applied to a respective combination of at least two control lines in the first set of control lines; and an array of second circuit elements, different to the memory elements, each connected to a control line of the first set of control lines and to another control line of a second set of control lines, different to the first set of control lines, so as to provide access to second circuit elements in the array.

Array of programmable memory elements with an array of second circuit elements

A power control integrated circuit is provided having a voltage switching device and a retention switching device that has an input from an overdrive voltage supply such that in a retention enabled configuration a retention switching device is switched on more strongly relative to being both coupled to and driven from the voltage supply input signal associated with the voltage switching device. An overdriven retention switching device is provided as a separate entity from the voltage switching device itself and a computer readable storage medium is provided storing a data structure comprising a standard cell circuit definition for use in generating validating the circuit layout of a circuit cell of an integrated circuit. The circuit cell comprising an overdriven retention switching device. A further data structure corresponding to a standard cell is provided comprising an overdriven retention switching device and a voltage switching device and yet a further standard cell data structure is provided comprising an overdriven voltage switching device.

Power controlling integrated circuit and retention switching circuit

An integrated circuit has a first and second voltage supply rails with first and second voltage levels and a gated voltage supply rail. Each of the circuit elements is connected either between the first and second voltage supply rails or between the gated rail and the second voltage rail. A source circuit structure comprising one or more circuit elements provides an input signal maintained at a static value during a power gated mode of operation. At least one recipient circuit structure requires receipt of the input signal at the static value during the power gated mode of operation. A distribution network comprises a first subset of circuit elements which pull their output to the first voltage level then the input signal has the static value, and a second subset of circuit elements which pull their output to the second voltage level when the input signal has the static value.

Growing community of inventors

Cambridge, United Kingdom

John Philip Biggs