Aeroflex Colorado Springs Inc.

Lsi Logic Corporation

John Pfeil

J Steve Griffith

Sam Stratton

Derek E Bass

A Data Throttling method duplicates the full-speed transmission of data so that it appears to be transmitting at a 10 Mhz rate. Additional storage elements and multiplexers are added along the data path but this completely eliminates undesirable complexity in the clock tree. In a two-bit application, data is received and transmitted two bits at a time, and yet the output 10 Mhz data rate is maintained. For an even ratio between the system clock rate and the 10 Mhz clock signal rate, bitis transmitted for half the time and bitis transmitted for the other half of the time. But if the full-speed clock rate is an odd multiple of 10 Mhz, then there will be a 'split cycle' including one bitand one bit

Data throttling circuit and method for a spacewire application

A PLL fail-over circuit technique and method to mitigate the effects of single-event transients comprises providing a pair of substantially identical phase-locked loops and producing a respective delayed clock signal from each. The outputs of the phase-locked loops are monitored for errors comprising high frequency transients or differences in clock signal outputs from a reference frequency. A clock out signal is output representative of the first delayed clock signal if an error is detected in the second phase-locked loop and the second delayed clock signal is output if an error is detected in the first phase-locked loop.

Phase-locked loop (PLL) fail-over circuit technique and method to mitigate effects of single-event transients

The amount of data transmitted in a primary data channel is increased by modulating a reference clock signal of the primary data channel with secondary data to form a separate secondary data channel. Primary data is formed into a primary data signal using the modulated reference clock signal, and a transmitter transmits the primary data signal to a receiver. The receiver recovers the primary data and modulated reference clock signal from the primary data signal, and then recovers the secondary data from the recovered modulated reference clock signal.

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Colorado Springs, CO, United States of America

John Pfeil