Intel Corporation

John Peter Stevenson

Chandan Egbert

Amin Firoozshahian

Mahesh Srinivasa Maddury

Omid Azizi

Andreas Kleen

Henk G Neefs

Alexandre Y Solomatnikov

Mahesh Madhav

David Hansen

Processing circuitry for computer memory management includes memory reduction circuitry to implement a memory reduction technique; and reference count information collection circuitry to: access a memory region, the memory region subject to the memory reduction technique; obtain an indication of memory reduction of the memory region; calculate metrics based on the indication of memory reduction of cache lines associated with the memory region; and provide the metrics to a system software component for use in memory management mechanisms.

Hardware-assisted paging mechanisms

Various systems and methods for computer memory management are described herein. A system for computer memory management includes a first memory device including a mapping table; a second memory device including a staging area; a third memory device including a dedup data region; and a controller operable to: receive a memory access request, the memory access request including an address and data; write the data to the staging area; and update the mapping table with the address.

Lazy memory deduplication

Growing community of inventors

Chicago, IL, United States of America

John Peter Stevenson