Texas Instruments Corporation

John Paul Tellkamp

Enis Tuncer

James Cooper Wainerdi

Andrew Patrick Couch

Rajen Manicon Murugan

Yiqi Tang

Satyendra Singh Chauhan

Tony Ray Larson

Akira Matsunami

Jie Chen

Usman Mahmood Chaudhry

Ming Li

Luigi Colombo

Anindya Poddar

Robert R Doering

Honglin Guo

Suvadip Banerjee

Chang-Yen Ko

Mahmud Halim Chowdhury

Clessie A Troxtell, Jr

Joe Adam Garcia

Amin Ahmad Sijelmassi

Murali Kittappa

A packaged multichip isolation device includes leadframe including a first and second die pad, with a first and second lead extending outside a molded body having a downward extending lead bend near their outer ends. A first integrated circuit (IC) die on the first die pad has a first bond pad connected to the first lead that realizes a transmitter or receiver. A second IC die on the second die pad has a second bond pad connected to the second lead that realizes another of the transmitter and receiver. An isolation component is in a signal path of the isolation device including a capacitive isolator, or inductors for transformer isolation on or between the die. A midpoint of the thickness of the die pad is raised above a top level of the leads and in an opposite vertical direction relative to the downward extending bend of the external leads.

Inverted leads for packaged isolation devices

A semiconductor isolation package includes a leadframe that includes a plurality of leadframe leads. At least one of the plurality of leadframe leads includes a lead body having a first end that comprises an external pin portion and a second end. The lead body has a leg portion coupled to a central lead portion that is coupled to an edge bend portion. The edge bend portion is formed by a first bend on the lead body proximate the second end between the central lead portion and edge bend portion. The first bend is in the direction of the first end on the leg portion. The edge bend assists in shielding electronic fields. Other aspects are presented.

Edge bend for isolation packages

In examples, a package comprises a semiconductor die having a device side and a bond pad on the device side, a conductive terminal exposed to an exterior of the package, and an electrical fuse. The electrical fuse comprises a conductive ball coupled to the bond pad, and a bond wire coupled to the conductive terminal. The bond wire is stitch-bonded to the conductive ball.

Packages with electrical fuses

An electronic device includes one or more multinode pads having two or more conductive segments spaced from one another on a semiconductor die. A conductive stud bump is selectively formed on portions of the first and second conductive segments to program circuitry of the semiconductor die or to couple a supply circuit to a load circuit. The multinode pad can be coupled to a programming circuit in the semiconductor die to allow programming a programmable circuit of the semiconductor die during packaging. The multinode pad has respective conductive segments coupled to the supply circuit and the load circuit to allow current consumption or other measurements during wafer probe testing in which the first and second conductive segments are separately probed prior to stud bump formation.

Multi-function bond pad

A leadframe includes leads or lead terminals, a plurality of folded features including i) support features positioned within an area defined in at least one dimension by the leads or the lead terminals configured for supporting at least one of a die pad and a first pad and a second pad spaced apart from one another, or ii) current carrying features. At least one of the folded features includes a planar portion and a folded edge structure that curves upwards at an angle of at least 45&#xb0; relative to the planar portion. The folded features are configured to provide an effective increase in thickness to reduce the deformation observed in assembly.

Leadframes with folded conductor portion and devices therefrom

A Hall-effect sensor package includes and an IC die including a Hall-Effect element and a leadframe including leads on a first side providing a first field generating current (FGC) path including&#x2265;1 first FGC input pin coupled by a reduced width first curved head over or under the Hall-effect sensor element to &#x2265;1 first FGC output pin, and second leads on a second side of the package. Some leads on the second side are attached to bond pads on the IC die including the output of the Hall-effect element. A clip is attached at one end to the first FGC input pin and at another end to a location on the first FGC output pin, having a reduced width second curved head in between that is over or under the Hall-effect sensor element opposite the first head.

Hall-effect sensor package with added current path

A Hall-effect sensor package includes and an IC die including a Hall-Effect element and a leadframe including leads on a first side providing a first field generating current (FGC) path including &#x2265;1 first FGC input pin coupled by a reduced width first curved head over or under the Hall-effect sensor element to &#x2265;1 first FGC output pin, and second leads on a second side of the package. Some leads on the second side are attached to bond pads on the IC die including the output of the Hall-effect element. A clip is attached at one end to the first FGC input pin and at another end to a location on the first FGC output pin, having a reduced width second curved head in between that is over or under the Hall-effect sensor element opposite the first head.

A method of testing an integrated circuit clearance distance device ('ICCDD') having a predetermined clearance distance in air requirement and a predetermined isolation voltage limit including calculating a value of the breakdown voltage at the predetermined clearance distance for at least one gas; and selecting a gas in which the ICCDD has a breakdown voltage that is less than the predetermined isolation voltage.

Testing of integrated circuits with external clearance requirements

An article of manufacture includes a semiconductor die () having an integrated circuit () on a first side of the die (), a diffusion barrier () on a second side of the die () opposite the first side, a mat of carbon nanotubes () rooted to the diffusion barrier (), a die attach adhesive () forming an integral mass with the mat () of the carbon nanotubes, and a die pad () adhering to the die attach adhesive and () and the mat () of carbon nanotubes for at least some thermal transfer between the die () and the die pad () via the carbon nanotubes (). Other articles, integrated circuit devices, structures, and processes of manufacture, and assembly processes are also disclosed.

Grown carbon nanotube die attach structures, articles, devices, and processes for making them

A method of making an IC device includes providing a stack of leadframe sheets each including a plurality of leadframes and an interleaf member interposed between adjacent ones of the leadframe sheets. The interleaf members include indicia that identifies the leadframes sheets. The stack of leadframe sheets is loaded onto an assembly machine. A first interleaf member is removed from the first leadframe sheet. The first leadframe sheet is transferred onto a mounting surface of the assembly machine. Semiconductor die are attached to leadframes on the first leadframe sheet. The method can include reading the indicia from the first interleaf member to determine a part number and lead finish for the first leadframe sheet, verifying the part number for the first leadframe sheet by comparing to a build list, and transferring the first leadframe sheet onto a mounting surface of the assembly machine only if the part number is verified.

Interleaf for leadframe identification

A method of assembling an electronic device and electronic packages therefrom. A die attach adhesive precursor is placed between a top surface of a workpiece and an IC die. The die attach adhesive precursor includes metal particles, a first plurality of first microcapsules having a polymerizable material inside, and a second plurality of second microcapsules having a polymerization agent inside to form a first polymer upon rupture of first and second microcapsules. A force sufficient to rupture at least a portion of the first plurality of first microcapsules and at least a portion of the second plurality of second microcapsules is applied to form a self-healing die attach adhesive wherein the first polymer binds the plurality of metal particles and the remaining microcapsules and secures the IC die to the top surface of the workpiece. The self-healing die attach adhesive generally includes at least 90 vol. % metal.

Packaged electronic device having metal comprising self-healing die attach material

A packaged surface-mount semiconductor device has the outer, un-encapsulated lead segments structured in five adjoining portions: The first portion protrudes from the encapsulation about horizontally; the second portion forms a convex bend downwardly; the third portion is approximately straight downwardly; the fourth portion forms a concave bend upwardly; and the fifth portion is straight horizontally. Each segment has across the width a first groove in the third portion, either on the bottom surface or on the top surface. Preferably, the groove is about 2 leadframe thicknesses vertically over the bottom surface of the fifth lead portion. When stamped, the groove may have an angular outline about 5 and 50 &#x3bc;m deep; when etched, the groove may have an approximately semicircular outline about 50 to 125 &#x3bc;m deep. A second groove may be located in the second segment portion; a third groove may be located in the transition region from the third to the fourth segment portions.

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Rockwall, TX, United States of America

John Paul Tellkamp