Hewlett Packard Enterprise Development LP

Hewlett-packard Development Company, L.p.

Solum, Inc.

Monsanto Technology LLC

Winfield Solutions, LLC

John Paul Strachan

Catherine Graves

Jianhua Yang

Miao Hu

Brent Buchanan

Le Zheng

Can Li

Ning Ge

Suhas Kumar

Martin Foltin

Richard Stanley Williams

Dejan S Milojicic

Gilberto Medeiros Ribeiro

Giacomo Pedretti

Amit S Sharma

Wei Guang Wu

Justin White

Nicholas Koshnick

Michael John Preiner

Paolo Faraboschi

Matthew D Pickett

Sergey Serebryakov

Zhiyong Li

Thomas Van Vaerenbergh

Wei Yi

Sai Rahul Chalamalasetti

Julien Borghetti

Marco Fiorentino

Philip John Kuekes

Craig William Warner

Feng Miao

Emmanuelle J Merced Grafals

Raymond G Beausoleil

Gary A Gibson

Naveen Muralimanohar

Kirk M Bresniker

Shih-Yuan Wang

David A Fattal

Warren Bruce Jackson

Sagi Varghese Mathai

Di Liang

Janice H Nickel

Kimberly Keeton

Nathaniel Quitoriano

Hans S Cho

Dmitri Borisovich Strukov

Ron Roth

Chin-Hui Chen

Marco Florentino

Kai-Mei Camilla Fu

Tsung-Ching Huang

Glen Eric Montgomery

Harvey White, Jr

Muhammad Shakeel Qureshi

Bassem Tossoun

Aalap Tripathy

Benjamin Feinberg

Thomas Maurits M Van Vaerenbergh

Noraica Davila

Noraica Davila Melendez

Antonio Carlos Torrezan De Sousa

Kivanc Ozonat

A technique for compressing an analog content addressable memory (CAM) array is provided. Random input data is applied to the analog CAM array, and an average measure of similarity is calculated for each output row of the analog CAM array. Rows of the analog CAM array that have measures of similarity that are close to each other can be eliminated, such as by removing similar rows or merging together similar rows. Thus, the analog CAM array size can be reduced without a loss in accuracy of a model stored on the analog CAM array.

Compression of analog content addressable memory

Systems and methods are provided for employing analog content addressable memory (aCAMs) to achieve low latency complex distribution sampling. For example, an aCAM core circuit can include an aCAM array. Amplitudes of a probability distribution function are mapped to a width of one or more aCAM cells in each row of the aCAM array. The aCAM core circuit can also include a resistive random access memory (RRAM) storing lookup information, such as information used for processing a model. By randomly selecting columns to search of the aCAM array, the mapped probability distribution function is sampled in a manner that has low latency. The aCAM core circuit can accelerate the sampling step in methods relying on sampling from arbitrary probability distributions, such as particle filter techniques. A hardware architecture for an aCAM Particle Filter that utilizes the aCAM core circuit as a central structure is also described.

CAMs for low latency complex distribution sampling

A system for facilitating an enhanced k-SAT solver is provided. The system can include a set of analog content addressable memory (aCAM) modules that can represent an expression in a conjunctive normal form (CNF), wherein a respective aCAM module corresponds to a clause of the expression. The system can also include a set of data lines that can provide input candidate values to the set of aCAM modules. A controller of the system can program the set of aCAM modules with respective analog values to represent the expression. The system can also include sensing logic block to determine a distance of a current solution from a target solution based on a combination of respective outputs from the set of aCAM modules. The controller can then iteratively modify an input value for a subset of data lines until the current solution converges based on a convergence condition.

Enhanced k-SAT solver using analog content addressable memory

Embodiments of the disclosure provide a system, method, or computer readable medium for providing a differentiable content addressable memory (aCAM) that implements an analog input analog storage and analog output learning memory. The analog output of the differentiable CAM can provide input to a learning algorithm, which may compute the gradients in comparison to historic values and reduce data inaccuracies and power consumption.

Differentiable content addressable memory

A crossbar array includes a number of memory elements. An analog-to-digital converter (ADC) is electronically coupled to the vector output register. A digital-to-analog converter (DAC) is electronically coupled to the vector input register. A processor is electronically coupled to the ADC and to the DAC. The processor may be configured to determine whether division of input vector data by output vector data from the crossbar array is within a threshold value, and if not within the threshold value, determine changed data values as between the output vector data and the input vector data, and write the changed data values to the memory elements of the crossbar array.

Acceleration of model/weight programming in memristor crossbar arrays

Embodiments of the disclosure provide a system, method, or computer readable medium for programming a target analog voltage range of an analog content addressable memory (aCAM) row. The method may comprise calculating a threshold current sufficient to switch a sense amplifier (SA) on and discharge a match line (ML) connected to a cell of the aCAM; and based on calculating the threshold current, programming a match threshold value by setting a memristor conductance in association with the target analog voltage range applied to a data line (DL) input. The target analog voltage range may comprise a target analog voltage range vector.

Iterative programming of analog content addressable memory

In some examples, a device includes a first processing core comprising a resistive memory array to perform an analog computation, and a digital processing core comprising a digital memory programmable with different values to perform different computations responsive to respective different conditions. The device further includes a controller to selectively apply input data to the first processing core and the digital processing core.

Resistive and digital processing cores

Systems are methods are provided for implementing an analog content addressable memory (analog CAM), which is particularly structured to allow for an amount of variance (fuzziness) in its search operations. The analog CAM may search for approximate matches with the data stored therein, or matches within a defined variance. Circuitry of the analog CAM may include transistor-source lines that receive search-variance parameters, and/or data lines that receive search-variance parameters explicitly within the search input data. The search-variance parameters may include an upper bound and a lower bound that define a range of values within the allotted amount of fuzziness (e.g., deviation from the stored value). The search-variance parameters may program (using analog approaches) the analog CAM to perform searches having a modifiable restrictiveness that is tuned dynamically, as defined by the input search-variance. Thus, highly efficient hardware for complex applications involving fuzziness are enabled.

Methods and systems for an analog cam with fuzzy search

An analog error correction circuit is disclosed that implements an analog error correction code. The analog circuit includes a crossbar array of memristors or other non-volatile tunable resistive memory devices. The crossbar array includes a first crossbar array portion programmed with values of a target computation matrix and a second crossbar array portion programmed with values of an encoder matrix for correcting computation errors in the matrix multiplication of an input vector with the computation matrix. The first and second crossbar array portions share the same row lines and are connected to a third crossbar array portion that is programmed with values of a decoder matrix, thereby enabling single-cycle error detection. A computation error is detected based on output of the decoder matrix circuitry and a location of the error is determined via an inverse matrix multiplication operation whereby the decoder matrix output is fed back to the decoder matrix.

Analog error detection and correction in analog in-memory crossbars

Systems and methods are configured to provide a first problem to be solved to a network of memristors. A second problem to be solved can be gradually provided to the network of memristors. Controlled noise can be applied to the network of memristors for at least a portion of time during which the second problem is 'gradually' provided to the network of memristors. A solution to the second problem can be determined.

Quantum-inspired algorithms to solve intractable problems using classical computers

Growing community of inventors

San Carlos, CA, United States of America

John Paul Strachan