Globalfoundries Inc.

Microsoft Technology Licensing, LLC

John Paul Rankin

Stacy J Garvin

John Francis Bulzacchelli

Kenneth Colin Dyer

Hayden Cranford

Embodiments of the present disclosure include techniques for calibrating analog-to-digital converters (ADCs), such as successive approximation register SAR ADCs. In one embodiment, a pattern is applied to the input of an ADC to produce digital output codes. Counts of the digital output codes are used detect errors and adjust a clock delay of a comparator in the ADC. In other embodiments, an ADC calibration circuit is coupled to a calibration algorithm executing on a remote server to calibrate one or more ADCs.

SAR analog-to-digital converter calibration

Circuits for an analog-to-digital converter and methods of operating an analog-to-digital converter. A resistor digital-to-analog converter (RDAC) has a first reference node coupled to a first current source, a second reference node coupled to a second current source, an input port configured to receive a first voltage, and an output port coupled to a buffer. The RDAC is configured to generate a second voltage including a first voltage shift from the first voltage and to supply the second voltage from the output port of the RDAC to the buffer.

Analog-to-digital converters with resistor digital-to-analog converters for reference voltage tuning

Circuits for a successive approximation register analog-to-digital converter and related methods. A global reference circuit includes a first super source follower (SSF) circuit having an input coupled to an output of a first current mirror and to a first adjustment circuit, and an operational amplifier having an input coupled to an output of the first SSF circuit and an output coupled to an input of the first current mirror. Local slices each include a second current mirror having an input coupled to the output of the operational amplifier, a second super source follower (SSF) circuit having an input coupled to an output of the second current mirror and to a second adjustment circuit. The first and second adjustment circuits may be configured to adjust a voltage at the input of the first SSF circuit and respective voltages at the input of the second SSF circuit of each local slice.

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Raleigh, NC, United States of America

John Paul Rankin