Motorola Corporation

John Paul Oliver

James C Baker

John Jerome Janssen

Alexandre Mallette

Christopher P Larosa

Bryan W Zancho

Denise Carol Riemer

Nectar Andrew Kirkiris

Alexandre Malette

Mymy Nguyen

A method and apparatus for channel estimation in a rake receiver of a CDMA communication system operates with a finite-impulse-response channel estimation filter with L taps and having a fixed delay. A pilot sequence of a received sequence of data from a channel of the communication system on the rake receiver is input. A quality of the channel of the communication system is determined using noise or Doppler measurements. These measurements are used in adjusting a bandwidth of the filter to accommodate the channel quality while keeping the fixed delay, which minimizes the delay buffer size. The filter is then used to operate on the received sequence of data to provide coherent modulation.

Channel estimation in a rake receiver of a CDMA communication system

A method in a wireless communications device, for example, 3Generation (3G) Universal Mobile Telephone System (UMTS) user equipment, including estimating () noise power of a signal, estimating signal power () of the signal, estimating a signal to noise ratio () based on the estimated noise power and the estimated signal power, and at least partially unbiasing () the estimated signal to noise ratio based on the interval over which the noise power is averaged.

Unbiased signal to interference ratio in wireless communications devices and methods therefor

The pulse-shaping look-up table with transient suppression ( ) avoids hard turn-on and turn-off transients by modifying word segments of initial and final digital words during transmission of a digital data sequence. A controller ( ) sends a mode signal and a digital data sequence to the pulse-shaping look-up table with transient suppression ( ). A mode buffer and command block ( ) uses the mode signal to control the creation of initial and final digital words created by a data buffer and control block ( ) from the digital data sequence. The digital words are used by a look-up table ( ) to create a sampled digital output waveform sequence. The pulse-shaping look-up table with transient suppression ( ) provides an accurate output waveform sequence with reduced spectral emissions even during start-up and shut-down of digital data transmissions.

Method for suppressing transients using a pulse shaping look-up table

A method in a code division multiple access communication system having network infrastructure and a plurality of mobile terminals, including transmitting ( ) composite signal comprising a synchronization signal and another non-orthogonal signal from the network infrastructure, receiving ( ) the composite signal at the plurality of mobile terminals of the code division multiple access communication system, and increasing forward link capacity of the code division multiple access communication system by canceling ( ) the synchronization signal from at least some of the plurality of mobile terminals.

Methods and communications terminals for increasing capacity CDMA communications networks

A method for estimating Doppler spread in mobile wireless communication devices, for example in CDMA or W-CDMA cellular communication systems, with improved noise immunity. The Doppler spread estimation is based on an estimated value of an autocorrelation or autocovariance at a first lag ( ) and at a second lag ( ), the magnitude of which is greater than the first lag. A first ratio is determined ( ) between a first difference ( ) and a second difference ( ). The estimated Doppler spread is generally proportional to a square root ( ) of the first ratio, and is scaled ( ) by a multiplicative factor that depends on whether the estimated function is an autocorrelation or autocovariance function.

Doppler spread/velocity estimation in mobile wireless communication devices and methods therefor

A transient-suppressing mode switch ( ) uses a state machine ( ) in conjunction with a soft switch ( ) to control a first mode signal sent from a first mode signal source ( ) to a first soft switch input and a second mode signal from a second mode signal source ( ) to a second soft switch input. When switching from a first mode to a second mode, the state machine delays the transition of the second mode signal from a constant zero value to a non-zero value until after the amplitude of the first mode signal at the first soft switch input has decayed to a sufficiently small value in order to reduce transients caused by switching.

Transient-suppressing mode switch

According to the present disclosure, an parallel formatted data signal is applied to an input (,), and the data signal is divided into a first data signal and a second data signal. The second data signal is applied to a logic delay element (,) to produce a delayed second data signal that is a delayed-in-time version of the first data signal. The first data signal is applied to a first parallel-to-serial converter (,), the delayed second signal is applied to a second parallel-to-serial converter (,), and first and second bit-serial data streams are produced. A controller (,) synchronizes an Arithmetic Logic Unit (,) to the first and second bit-serial data streams so that the ALU (,) scales and sums the first and second bit-serial data streams to produce a bit-serial, sample-rate converted, output signal.

Fractional decimator with linear interpolation and method thereof

The pulse-shaping look-up table with transient suppression (530) avoids hard turn-on and turn-off transients by modifying word segments of initial and final digital words during transmission of a digital data sequence. A controller (570) sends a mode signal and a digital data sequence to the pulse-shaping look-up table with transient suppression (530). A mode buffer and command block (560) uses the mode signal to control the creation of initial and final digital words created by a data buffer and control block (550) from the digital data sequence. The digital words are used by a look-up table (540) to create a sampled digital output waveform sequence. The pulse-shaping look-up table with transient suppression (530) provides an accurate output waveform sequence with reduced spectral emissions even during start-up and shut-down of digital data transmissions.

Pulse-shaping look-up table with transient suppression

Delayed versions of a bit-serial input sequence are created. When the interpolation involves scaled versions of the input sequence, scaled versions of the input sequence are produced. The interpolation equations are implemented by adding the delayed versions of the input sequence and the scaled versions of the input sequence together. The sign bit of each of the equated interpolation terms are applied to a multiplexer (528), and the sign bits are sequentially produced at the multiplexer output (529). The multiplexed sign bits are sequentially latched to the output of a latch (534) to produce the bit-serial interpolation with sliced output signal.

Bit-serial linear interpolator with sliced output

According to the present disclosure, aperiodic data is applied to parallel register (500). When a predetermined relationship between an aperiodic load signal and a periodic oversample clock signal occurs, the aperiodic data is latched to the output (506) of the parallel register as substantially periodic data. The substantially periodic data is loaded into a sigma-delta DAC (502) for processing. The sigma-delta DAC (502) is driven by a periodic oversample clock to produce a 1-bit oversampled, time averaged representation of the substantially periodic data.

Method and apparatus for sigma-delta demodulator with aperiodic data

A bit-serial compressor (106) has a pre-divider circuit (208) receiving input serial data and generating a partial numerator. Divider circuit (210) divides the partial numerator by a denominator and generates a partial remainder that is fed back to the pre-divider circuit (208). Divider circuit (210) also generates serial data that is sent to an absolute value circuit (216) and then to a bit-serial filter (218). Bit-serial filter (218) generates an average signal from the serial data. A comparator circuit (224) compares the average signal to a threshold signal and generates the greater of the average signal or the threshold signal for use as a denominator in a next division cycle. The divider circuit includes an overflow control circuit (618) which detects overflow from the carryout bit of the partial remainder operation at the beginning of a division cycle and the sign bit of the numerator. If overflow is detected, the output is clipped according to whether the numerator is positive or negative.

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Chicago, IL, United States of America

John Paul Oliver