Cadence Design Systems, Inc.

John Paul Decker

Yaron Kashai

Dan Leibovich

Neyaz Khan

Efrat Shneydor

Arik Shmayovitsh

The present disclosure relates to a computer-implemented method for automatically generating a power management verification component. The method may include receiving one or more inputs including a power intent definition. The method may further include automatically generating a power management verification environment based upon, at least in part, the power intent definition, the power management verification environment including at least one of a driver and a monitor.

System, method, and computer program product for automatic power management verification

A method for modeling power management in an integrated circuit (IC) includes: specifying a circuit design and a power architecture for the IC, the power architecture including a plurality of power domains for specifying power levels in different portions of the IC; determining a testbench for simulating the IC and a verification plan for evaluating simulation results; using the testbench to simulate variations in power levels of the power domains of the IC; and using the verification plan to evaluate the simulation results for the power domains of the IC.

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Annandale, NJ, United States of America

John Paul Decker