Analog Devices,inc.

John Patrick Purcell

Anthony Gerard Scanlan

Vincent James Troy

Kieran K Heffernan

Martin Gerard Cotter

Joseph Michael Barry

Brian S Carroll

A method and a processor for processing two digital video signals clocked by respective clock signals of identical frequency but with a constant phase shift therebetween. Standard definition and progressive scan digital video signals which are clocked at first and second clock signals CLOCKand CLOCK, respectively, of identical frequency with a constant phase shift therebetween are interfaced with a processing circuit () by an interface circuit (). The progressive scan signal is clocked into a first register () on the second clock signal CLOCK, and is clocked to a second register () by the first clock signal CLOCKand in turn to a third register () by the first clock signal CLOCK. The edge of the first clock signal CLOCKon which the progressive scan signal is clocked into the second register () is chosen to allow sufficient time to clock the signal. The standard definition signal is clocked through fourth, fifth and sixth registers (), respectively, and both signals are clocked from the third and sixth registers () on the first clock signal CLOCKinto the processing circuit ().

Method and a processor for processing two digital video signals clocked by respective clock signals of identical frequency but with a constant phase shift therebetween

A multi-channel circuit ( ) comprising three channels (CH to CH ), each of which is provided with a current steering DAC ( ) in which crosstalk between the respective DACs ( ) is minimized. Each DAC ( ) comprises binary scaled current source devices (Q to Q ) and current steering switches (Q and Q to Q to Q ) for steering currents from the current source devices (Q to Q ) to summing nodes ( ) across which an analogue signal is developed corresponding to a digital input word. Cascode devices (Q to Q ) are provided between the respective current source devices Q to Q and the corresponding current steering switches (Q and Q to Q and Q ) for preventing capacitive feedthrough of voltage swings on the current steering switches (Q and Q to Q and Q ) for minimizing crosstalk between the DACs ( ). Gates of the cascode devices (Q to Q ) of DACs ( ) are biased from corresponding cascode bias voltage circuits ( ), and the gates of the cascode devices (Q to Q ) of each DAC ( ) are isolated from the gates of the cascode devices (Q to Q ) of the other DACs ( ) also for minimizing crosstalk.

Multi-channel circuit with current steering digital to analogue converters with minimized crosstalk

A method for converting multi-bit digital video data signals to analogue form wherein the video data signals are in three formats, namely, standard definition, progressive scan and high definition formats, which permits a relatively low order analogue reconstruction filter to be used for filtering the analogue form of the signal. The three formats of the digital video data signals are over-sampled at relatively low over-sampling rates, the standard definition video signals being over-sampled at eight times the nyquist sampling frequency, the progressive scan format signals being over-sampled at four times the nyquist sampling frequency, while the high definition format signals are over-sampled at twice the nyquist sampling frequency. By virtue of the fact that the Video data signals are over-sampled at relatively low over-sampling rates, the over-sampled signals are subjected to sigma-delta modulation in a relatively low order sigma-delta modulator, namely, a second order sigma-delta modulator for noise shaping the quantisation noise. This, thus, permits the analogue reconstruction filter to be provided as a third order filter, and thus of relatively low order.

Method for converting a video signal from one of an analogue and digital form to the other of the analogue and digital form with enhanced signal to noise ratio

A detector circuit ( ) for detecting the presence or absence of a television ( ) on an output ( ) of a video DAC ( ) comprises a comparator ( ) for comparing a voltage developed by the video signal on a control resistor R with a reference voltage of 0.5 volts. The resistor R is of 75 ohms and matches the internal impedance R of 75 ohms of the television ( ). A latch ( ) latches the output from the comparator ( ) onto an output pin Q when the voltage developed across the control resistor R is developed by an equalisation pulse of the vertical blanking interval of the video signal. In the presence of a television ( ) the voltage developed across the control resistor R is 0.35 volts, which pulls the output of the comparator ( ) low, while in the absence of a television ( ) the voltage developed across the control resistor R is 0.7 volts which pulls the output of the comparator ( ) high. A control logic control circuit ( ) reads the output pin Q of the latch ( ) for powering up or powering down the video DAC ( ) as appropriate.

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Limerick, Ireland

John Patrick Purcell