Gm Global Technolgoy Operations, Inc.

University of Michigan

John Patrick Hayes

Brian Thomas Murray

Krishnendu Chakrabarty

Younggap You

A circuit with a built-in self test, comprising: a circuit to be tested; a generating circuit coupled to the circuit to be tested, wherein the generating circuit generates (i) a series of input signals to the circuit to be tested and (ii) a series of reference signals; a space compaction circuit coupled to an output of the circuit to be tested, wherein the space compaction circuit uses a categorized response of the circuit to be tested to compact the output of the circuit to be tested by a maximum ratio and produces a series of output signals when the input signals are applied to the circuit to be tested; an analysis circuit coupled to the space compaction circuit and the generating circuit, providing a signal indicative of error in the circuit to be tested when the output signals fail to correspond to the reference signals.

Circuit with built-in test and method thereof

Very large dynamic RAM integrated circuits are rendered self-testing by using on-chip generation of data test patterns with very high fault coverage, and concurrent testing of storage cell subarrays to reduce overall testing time. A test generator, which may operate in combination with the refresh control and timing system of the RAM integrated circuit, supplies the initial data test pattern which is loaded into the storage arrays. The conventional sense amplifier array is modified, and coupled with a gate control system for shifting data in each column of each storage subarray to an adjacent column. Alternatively, a two-terminal bilateral storage cell may be used to effect the shifting function, which effectively converts the memory into a shift register. The use of complementary data test patterns will permit detection of symmetrical faults within storage arrays.

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Ann Arbor, MI, United States of America

John Patrick Hayes