North American Philips Corporation

Philips Electronics North America Corporation

Sigma Designs, Inc.

Telcom Semiconductor, Inc.

Greenvity Communications, Inc.

John P Tero

Johan Hendrik Huijsing

Hung C Nguyen

Ali Tasdighi

Ronald Hogervorst

Catherine A French

Shaoan Chin

Bing F Ma

Jayesh Desai

Ruoyang Lu

Amado A Caliboso

Roelof F Wassenaar

Remco J Wiegerink

Ron Hogervorst

Junjie Yang

Can Tri Nguyen

A switched-capacitor amplifier comprises an operational amplifier (op-amp), a first capacitor, a second capacitor, a third capacitor, a fourth capacitor and a plurality of switches connected to these capacitors. The first capacitor equals the third capacitor, the second capacitor equals the fourth capacitor, and the first capacitor is asymmetric to the second capacitor, the third capacitor is asymmetric to the fourth capacitor. A ratio of the first capacitor and the second capacitor is a function of a simulated parasitic capacitance of the switched-capacitor amplifier, a simulated DC gain of the operational amplifier, and a target gain of the switched-capacitor circuit.

Method of producing low-power switched-capacitor amplifier, circuit and a pipeline analog-to-digital converter including the same

A system connected to power lines in a network includes a wireless component; a wired component interfaced with the power lines; a conversion component coupled to the wireless component and the wired component and performs at least unidirectional conversion of a transmission unit between wireless and wired, the conversion employs only MAC addresses for addressing.

System and method for communications in a network

ADC accuracy is increased by 1 bit by interpolation of comparator outputs in a comparator array, thereby increasing accuracy without significantly increasing power consumption and size. Specifically, an analog-to-digital converter includes a binary converter and a comparator array, which comprises a plurality of comparator blocks, each block having a primary comparator and an interpolating comparator. The interpolating comparator compares an output signal from the primary comparator with a negative output signal from a primary comparator of another block of the plurality of blocks to generate a least significant bit. The binary converter, which is coupled to the array, converts array output to binary code.

Extension of accuracy of a flash ADC by 1-bit through interpolation of comparator outputs

The invention enables automatic gain control in ultra wideband applications over multiple channels and frequency bands.

Digital automatic gain control with parallel/serial interface for multiple antenna ultra wideband OFDM system

ADC accuracy is increased by 1 bit by interpolation of comparator outputs in a comparator array, thereby increasing accuracy without significantly increasing power consumption and size. Specifically, an analog-to-digital converter includes a binary converter and a comparator array, which comprises a plurality of comparator blocks, each block having a primary comparator and an intepolating comparator. The intepolating comparator compares an output signal from the primary comparator with a negative output signal from a primary comparator of another block of the plurality of blocks to generate a least significant bit. The binary converter, which is coupled to the array, converts array output to binary code.

A charge pump circuit including two transfer capacitors, two reservoir capacitors and a plurality of switches. The transfer capacitors are charged to Vin when the charge pump circuit is in a first operating state, the transfer capacitors are connected in a first series arrangement to apply a +2 Vin charge to one of the reservoir capacitors when the charge pump circuit is in a second operating state, and the transfer capacitors are connected in a second series arrangement to apply a -2 Vin charge to the other of the reservoir capacitors when the charge pump circuit is in a third operating state. A control circuit is provided to control the plurality of switches such that the charge pump circuit enters the first through third operating states is a predetermined sequence.

Charge pump circuit having independent inverted and non-inverted

A fixed and a user adjustable voltage reference is alternatively provided by an integrated switch which switches between two current sources according to an input voltage. A fixed reference voltage is achieved by amplifying the current of one of the two current sources according to a predetermined voltage difference between the output terminal and an internal reference voltage. An adjustable reference voltage is achieved by amplifying the current of other of the two current sources according to a voltage difference between the internal reference voltage and an user adjustable voltage. In one embodiment, the user adjustable voltage is achieved by a user adjustable voltage divider circuit.

Integrated switch for selecting a fixed and an adjustable voltage

Compact g.sub.m -control circuits for CMOS rail-to-rail input stages operating in strong inversion are provided. The G.sub.m -control circuit makes the sum of the gate-source voltages of the complementary input transistors, and therefore the g.sub.m of the input stage constant. The compact g.sub.m -control circuits implement a floating voltage source in the form of circuit elements between the N and P-channel input stage transistors and the positive and negative supply rails of the operational amplifier.

Compact GM-control for CMOS rail-to-rail input stages by regulating the

A transconductance (g.sub.m) control circuit for bipolar or CMOS rail-to-rail input stages is provided. The g.sub.m is controlled by the use of multiple input pairs and can be used in CMOS or bipolar technology. In CMOS the g.sub.m -control works regardless of the operating region of the MOS transistor, whether it is weak, moderate or strong inversion.

Rail-to-rail input stages with g.sub.m -control by multiple input pairs

A differential amplifier contains a pair of differential portions (10 and 12) that together provide representative signal amplification across the full amplifier power-supply voltage range. Each differential portion normally contains a pair of like-polarity differentially coupled FETs (Q1 and Q2, Q3 and Q4) that divide a tail current (I.sub.N, I.sub.P) into a pair of main currents (I.sub.1 and I.sub.2, I.sub.3 and I.sub.4). The two FET pairs are complementary. A square-root circuit (24) controls the tail currents in such a way that the sum of their square roots is largely constant. Consequently, the amplifier transconductance is largely constant.

Differential amplifier having rail-to-rail input capability and

A combination driver/summing circuit for rail-to-rail operation of a differential amplifier includes a differential amplifier input stage that amplifies an input signal and a current control circuit that regulates the operating currents through the active elements of the differential amplifier input stage. A summing circuit divided into first and second segments and supplied with current from a single common floating current source combines internal currents supplied by the differential amplifier input stage. A class A-B driver/output stage is coupled to the summing circuit to derive at least one output signal representative of the input signal and which is operative over nearly the full rail-to-rail supply voltage range.

Combination driver-summing circuit for rail-to-rail differential

An output circuit having the output taken between a pull-up output transistor and a pull-down output transistor connected in series for conducting current alternatively. Separate pull-up and pull-down driver circuits are controlled by a common input signal. The pull-down driver circuit is supplied by a pull-down current source, and a diode is connected from the point between the pull-down driver transistor and pull-down current source to the output node. The effect of a large node capacitance is reduced by the diode, which conducts current from the pull-down current source to any output load capacitance to raise the output voltage more rapidly when the pull-down driver circuit is cut off.

Totem pole circuit with additional diode coupling

A differential amplifier contains first and second differential portions (20 and 22) that operate together to achieve rail-to-rail input amplification capability. A main current supply (6) provides a main supply conduit (I.sub.L) for the two differential portions. The circuit transconductance is controlled in a desired manner with a control amplifier (AN) suitably coupled to the differential portions and main current supply. A current-steering circuit typically formed with a pair of voltage clamps (30 and 32) enables a pair of level-shift current supplies (16 and 18) in the second differential portion to remain conductive as the input common-mode voltage traverses the entire supply voltage range. Consequently, the differential amplifier achieves a very fast response to changes in the input voltage difference irrespective of the value of the input commond-mode voltage.

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Saratoga, CA, United States of America

John P Tero