Honeywell Information Systems Inc.

Bull Hn Information Systems, Inc.

John P Stafford

Joseph L Ryan

Richard R Watkins

Nicholas R Long

Minoru Inoshita

Frederick E Kobs

Gerald N Winfrey

William E Peisel

Richard A Slater

Allen B Cuccio

Gerald A Lief

Jerold M Zelinsky

A host computer stores data and attribute bytes for display on a terminal or personal computer having a monochrome screen. The monochrome attributes include low intensity, underline, inverse, blink and hide. The host computer may communicate with a terminal or personal computer having a color screen without modifying the host program or the data and attribute bytes. The terminal or personal computer operator may determine the color and attribute for each of the monochrome attributes.

Emulation attribute mapping for a color video display

A logic system is provided in a video system for accommodating the display of both video data characters and graphic characters, and the application of visual attributes to such characters whether occurring singularly or in fields.

Character generator display system

A logic system is provided in a video system for accommodating the display of video data characters and the application of visual attributes to such characters whether occurring singularly or in fields.

Data character video display system with visual attributes

Apparatus in a Cathode Ray Tube (CRT) display allows the sharing of the system bus between the microprocessor (CPU) and Direct Memory Access (DMA) devices without degrading the CPU performance by splitting the system bus cycle into an address phase and a data phase.

Split system bus cycle for direct memory access of peripherals in a

A cathode ray tube display terminal system includes a central processor subsystem and a number of certain peripheral subsystems all of which are coupled in common to a system bus. Apparatus in the central processor subsystem receives interrupt request signals from certain of the peripheral subsystems and on a predetermined priority basis modifies an address generated by the central processor subsystem in dependence upon which of the requesting certain peripheral subsystems has the highest priority. The modified address, called a vectored address points to a firmware subroutine stored in a memory subsystem which is also coupled to the system bus and which processes the interrupt from the highest priority cetain peripheral subsystem. Other peripheral subsystems coupled to the system bus generate a single interrupt signal which is also applied to the apparatus in the central processor system. The highest priority other peripheral subsystem generating the single interrupt signal responds to an interrupt acknowledge signal from the central processor subsystem by sending address signals to the apparatus which are used to modify the address generated by the central processing subsystem so as to produce the vectored address.

CRT display terminal priority interrupt apparatus for generating

A control unit controls a data processing system port to communicate with different peripheral devices. The control unit determines the type of peripheral device that is being serviced and whether the port apparatus is transmitting or receiving data, and accordingly, activates a program to load a particular count into a counter. Upon reaching a specified count, the counter activates the control unit to control the sampling time of the incoming signal and to determine the interval of time or frequency of the transmitted data information signals.

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Nashua, NH, United States of America

John P Stafford