Spinnaker Semiconductor, Inc.

Avolare 2, LLC

Granbluetech, L.l.c.

Soligie, Inc.

John P Snyder

John M Larson

John M Heitzinger

John P Larson

An apparatus and associated method for an energy-storage device (e.g., a capacitor) having a plurality of electrically conducting electrodes including a first electrode and a second electrode separated by a non-electrically conducting region, and wherein the non-electrically conducting region further includes a non-uniform permittivity (K) value. In some embodiments, the method includes providing a substrate; fabricating a first electrode on the substrate; and fabricating a second electrode such that the second electrode is separated from the first electrode by a non-electrically conducting region, wherein the non-electrically conducting region has a non-uniform permittivity (K) value. The capacitor devices will find benefit for use in electric vehicles, of all kinds, uninterruptible power supplies, wind turbines, mobile phones, and the like requiring wide temperature ranges from several hundreds of degrees C. down to absolute zero, consumer electronics operating in a temperature range of &#x2212;55 degrees C. to 125 degrees C.

Vacuum-capacitor method and apparatus

Vacuum-capacitor apparatus and method

Method and associated capacitors having engineered electrodes with very high energy density

Capacitors having engineered electrodes with very high energy density and associated method

Capacitors having engineered electrodes with very high energy density

Method and apparatus for capacitors having engineered electrodes with very high energy density

Apparatus and method for capacitors having engineered electrodes with very high energy density

A CMOS device and method of fabrication are disclosed. The present invention utilizes Schottky barrier contacts for source and/or drain contact fabrication within the context of a CMOS device and CMOS integrated circuits, to eliminate the requirement for halo/pocket implants, shallow source/drain extensions to control short channel effects, well implant steps, and complex device isolation steps. Additionally, the present invention eliminates the parasitic bipolar gain associated with CMOS device operation, reduces manufacturing costs, tightens control of device performance parameters, and provides for superior device characteristics as compared to the prior art. The present invention, in one embodiment, uses a silicide exclusion mask process to form the dual silicide Schottky barrier source and/or drain contact for the complimentary PMOS and NMOS devices forming the CMOS device.

Schottky barrier CMOS device and method

A CMOS device and method of manufacture is provided for producing an integrated circuit that is not susceptible to various soft errors such as single-event upsets, multi-bit upsets or single-event latchup. The CMOS device and method utilizes a new and novel well architecture in conjunction with metal source/drain electrodes to eliminate soft errors. In one embodiment, the CMOS device uses a first metal source/drain material for the NMOS device and a second metal source/drain material for the PMOS device. The CMOS device further uses a multi-layered well-structure with a shallow N-well and a buried P-well for the PMOS device and a shallow P-well and a buried N-well for the NMOS device.

Method of manufacturing a CMOS device with zero soft error rate

A device for regulating a flow of electric current and its manufacturing method are provided. The device includes metal-insulator-semiconductor source-drain contacts forming Schottky barrier or Schottky-like junctions to the semiconductor substrate. The device includes an interfacial layer between the semiconductor substrate and a metal source and/or drain electrode, thereby dynamically adjusting a Schottky barrier height by applying different bias conditions. The dynamic Schottky barrier modulation provides increased electric current for low drain bias conditions, reducing the sub-linear turn-on characteristic of Schottky barrier MOSFET devices and improving device performance.

Dynamic Schottky barrier MOSFET device and method of manufacture

Systems and methods of fabricating silicon-based thin film transistors (TFTs) on flexible substrates. The systems and methods incorporate and combine deposition processes such as chemical vapor deposition and plasma-enhance vapor deposition, printing, coating, and other deposition processes, with laser annealing, etching techniques, and laser doping, all performed at low temperatures such that the precision, resolution, and registration is achieved to produce a high performing transistor. Such TFTs can be used in applications such as displays, packaging, labeling, and the like.

Silicon thin film transistors, systems, and methods of making same

The invention is directed to a device for regulating the flow of electric current with high dielectric constant gate insulating layer and a source and/or drain forming a Schottky contact or Schottky-like region with a substrate and its fabrication method. In one aspect, the gate insulating layer has a dielectric constant greater than the dielectric constant of silicon. In another aspect, the current regulating device may be a MOSFET device, optionally a planar P-type or N-type MOSFET, having any orientation. In another aspect, the source and/or drain may consist partially or fully of a silicide.

Metal source and drain transistor having high dielectric constant gate insulator

The present invention is a field effect transistor having a strained semiconductor substrate and Schottky-barrier source and drain electrodes, and a method for making the transistor. The bulk charge carrier transport characteristic of the Schottky barrier field effect transistor minimizes carrier surface scattering, which enables the strained substrate to provide improved power and speed performance characteristics in this device, as compared to conventional devices.

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Edina, MN, United States of America

John P Snyder