Intel Corporation

John P Shen

Hong Wang

Perry H Wang

Per H Hammarlund

Gautham N Chinya

James Paul Held

Steve Shih-wei Liao

Edward Thomas Grochowski

Xiang Chris Zou

Xinmin Tian

Milind Baburao Girkar

Bryant E Bigbee

Partha Kundu

Jamison D Collins

Tin-Fook Ngai

Raya Leviathan

Baiju V Patel

Shivnandan D Kaushik

Richard A Hankins

Gerolf F Hoflehner

Prashant Sethi

Daniel M Lavery

Ryan N Rakvic

Quinn Able Jacobson

Trung Am Diep

Piyush N Desai

Tor M Aamodt

Kshitij Arun Doshi

Gad Shlomo Sheaffer

Matthew C Merten

Sanjiv M Shah

Suresh Srinivas

Anne Weinberger Bracy

Ali-Reza Adl-Tabatabai

Scott Dion Rodgers

Bratin Saha

Asit K Mallick

George Zacharias Chrysos

Doron Orenstein

Jared Warner Stark, Iv

Paul M Petersen

Pedro Marcuello

Deepak Limaye

Shih-wei Liao

Dongkeun Kim

Bohuslav Rychlik

Jeffery A Brown

Christopher B Wilkerson

Ittai Anati

Wei Ey Li

Antonio Gonzalez

Chris J Newburn

Robert Geva

Bryan P Black

Antonio González

Robert P Knight

David K Poulsen

Ed Grochowski

Ali-Reza Adi-Tabatabai

Shirish Aundhe

Jared W Stark

Marsha Eng

William R Greene

Jim B Crossland

Anil Aggawal

Jamison D Colins

Gautham Shinya

Bratin Saba

Geolf F Hoflehner

Ashok N Seshadri

Anthony N Mah

Ravi K Chandran

Sriram Vajapeyam

Ralph M King

Method, apparatus, and program means for a programmable event driven yield mechanism that may activate other threads. In one embodiment, an apparatus includes execution resources to execute a plurality of instructions and a monitor to detect a condition indicating a low level of progress. The monitor can disrupt processing of a program by transferring to a handler in response to detecting the condition indicating a low level of progress. In another embodiment, thread switch logic may be coupled to a plurality of event monitors which monitor events within the multithreading execution logic. The thread switch logic switches threads based at least partially on a programmable condition of one or more of the performance monitors.

Programmable event driven yield mechanism which may activate other threads

A method and system to provide user-level multithreading are disclosed. The method according to the present techniques comprises receiving programming instructions to execute one or more shared resource threads (shreds) via an instruction set architecture (ISA). One or more instruction pointers are configured via the ISA; and the one or more shreds are executed simultaneously with a microprocessor, wherein the microprocessor includes multiple instruction sequencers.

Method and system to provide user-level multithreading

In an embodiment, a method is provided. The method includes managing user-level threads on a first instruction sequencer in response to executing user-level instructions on a second instruction sequencer that is under control of an application level program. A first user-level thread is run on the second instruction sequencer and contains one or more user level instructions. A first user level instruction has at least 1) a field that makes reference to one or more instruction sequencers or 2) implicitly references with a pointer to code that specifically addresses one or more instruction sequencers when the code is executed.

Mechanism for instruction set based thread execution on a plurality of instruction sequencers

Method and system to provide concurrent user-level, non-privileged shared resource thread creation and execution

Method, apparatus and system embodiments to schedule OS-independent 'shreds' without intervention of an operating system. For at least one embodiment, the shred is scheduled for execution by a scheduler routine rather than the operating system. A scheduler routine may run on each enabled sequencer. The schedulers may retrieve shred descriptors from a queue system. The sequencer associated with the scheduler may then execute the shred described by the descriptor. Other embodiments are also described and claimed.

Mechanism to schedule threads on OS-sequestered sequencers without operating system intervention

A technique to monitor software thread performance and update software that issues or uses the thread(s) to reduce performance-inhibiting events. At least one embodiment of the invention uses hardware and/or software timers or counters to monitor various events associated with executing user-level threads and report these events back to a user-level software program, which can use the information to avoid or at least reduce performance-inhibiting events associated with the user-level threads.

Mechanism for monitoring instruction set based thread execution on a plurality of instruction sequencers

A technique for using memory attributes to relay information to a program or other agent. More particularly, embodiments of the invention relate to using memory attribute bits to check various memory properties in an efficient manner.

Technique for using memory attributes

Method, apparatus, and system for a programmable event-driven yield mechanism. The mechanism may disrupt processing of a program to deliver a yield event. The event may be treated as a fault-like yield event or a trap-like event. For a fault-like yield event, the faulting instruction is canceled before retirement and processor state is not updated before the yield event is delivered. For a trap-like yield event the instruction causing the trap is retired and the yield event is delivered on an interrupt boundary. Multiple pending yield events may be handled according to priority. Other embodiments are also described and claimed.

Programmable event-driven yield mechanism

Growing community of inventors

San Jose, CA, United States of America

John P Shen