Cirrus Logic Inc.

Microtune (texas), Inc.

Microtune, Inc.

John P Norsworthy

Bruce A Doyle

Douglas J Bartek

Jaideep Prakash

Stanley Vincent Birleson

Jay A Thompson

A multiple information decoding system and method are provided in which multiple information content is decoded sequentially and provided to a viewer such that the viewer perceives the information content as being simultaneously decoded. One embodiment of the system and method is in a video display system where RF channels are decoded by a single tuner for concurrent presentation to a display.

System and method for providing fast acquire time tuning of multiple signals to present multiple simultaneous images

The invention is a multiple mode transmission system that interconnects the computer of a user with the Internet. The system has a first link that is a relatively low bandwidth telephone system. The system also has a second link that is a relatively high bandwidth television system. The television link can be either terrestrial or cable. The user would send an information request to the Internet across the telephone system. The actual information would be sent to the user via the television system. Scheduling data that informs the user of the time, channel, and exact location of the information in the television signal is sent to the user across the telephone system. The scheduling data is used by the inventive system to program the TV tuner that is used by the computer to receive the TV signal. The information can be encrypted, and the key would be included with the scheduling data. The channels can be dedicated data channels. A plurality of users would share the television system, and each user is only temporarily assigned a portion of the channel.

Internet transaction acceleration

A precise current cell for a digital-to-analog (D/A) convertor circuit is designed to compensate for manufacturing process variations. The cell uses a cascoded transistor chain to control the output voltage and isolate voltage supply noise. An external (off-chip) bias current is fed into a cascoded biasing string of eight transistors, which are further mirrored to the current cell itself. The biasing scheme accounts for manufacturing process variations in the chip, which leads to very precise current being replicated at the output of the D/A circuit. Current steering and an improved shunt path within the current cell minimizes voltage swings during switching of the current cell. This allows for faster switching of the cell while minimizing noise coupling due to the voltage swings. The current cell also has an associated biasing stage. This biasing stage allows for improved matching within the current cell, resulting in improved accuracy of conversion. Additionally, the biasing circuit minimizes noise coupling from ground potential to the D/A convertor output. A reset circuit is also included. This current cell, associated biasing stage, and reset circuit is suitable for applications requirement precise D/A conversions at high speeds.

Two cascoded transistor chains biasing DAC current cells

Disclosed is a system and method for providing full monotonicity among desired sequential output values by converting a stream of sequential input signals each of which are representative of their corresponding desired output values. The disclosed invention comprises a system and method for individually translating each received signal to a unary value, the unary value being representative of a desired output value, and a system and method for selectively enabling a plurality of energy sources as a function of this unary value such that the total of any enabled energy source at any one time is proportional to this unary value. The conversion circuit uses a shifting array for controlling the energy sources.

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Lucas, TX, United States of America

John P Norsworthy