International Business Machines Corporation

John P Norsworthy

Gene J Gaudenzi

Nghia Van Phan

Allan Harvey Dansky

Frank A Montegari

Dennis C Banker

Dennis C Reedy

The invention pertains to semiconductor circuitry, and more particularly to a class of circuitry known as current controlled gate circuits for driving very large scale integrated circuit gate arrays; the novel circuit can achieve much lower speed-power products than other circuitry, such as the well known T.sup.2 L circuitry; the circuit includes push-pull drive and it provides negligible DC current in both DC states, that is, On and Off.

High speed low power current controlled gate circuit

Power dissipation in an off-chip driver circuit is decreased by utilizing a selectively switched transistor to discharge the base of the output pull-down transistor, and by using a large resistance in the base current path for the first stage of the Darlington pull-up transistors. An additional transistor having a larger emitter area and coupled to a lower potential source is connected in parallel with the normal phase-splitter transistor to provide additional output current sinking capability, and a current mirror is connected to control the current through both the phase splitting transistor and the additional transistor to control the turn-on transition of the pull-down output transistor.

Low power off-chip driver circuit

Logic circuit means for providing a binary output which is a predetermined logical function of a plurality of binary inputs, said logic circuit means including: at least first, second and third push-pull Darlington current sink (PPDCS) logic circuits, each said PPDCS logic circuit comprising: first, second and third transistors, each of said first, second and third transistors having an emitter, base and collector, said collector of said third transistor connected to a first source of potential and said emitter of said second transistor connected to a third source of potential; input circuit means, said input circuit means being adapted to receive n binary inputs, where n is a positive integer having a magnitude of two or greater, said input circuit means being connected to said collector of said first transistor and said base of said third transistor; a first resistor connected between said emitter of said first transistor and a second source of potential; a second resistor connected between said first source of potential and a common connection of said base of said first transistor and said base of said second transistor; a third resistor connected between said base of said third transistor and said first source of potential; a first diode connected across said base-collector junction of said first transistor; a second diode connected across said base-collector junction of said second transistor; output circuit means connected in common to said collector of said second transistor and said emitter of said third transistor, said output circuit means electrically manifesting the logical binary NOR function of said n binary inputs received by said input circuit means; and interconnection means interconnecting the output circuit means of each of said at least first, second and third PPDCS circuits, said interconnection means including an output terminal for manifesting said binary output of said logic circuit means.

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Fishkill, NY, United States of America

John P Norsworthy